Commit 7c348d8d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'socfpga_dts_update_for_v5.12' of... 

Merge tag 'socfpga_dts_update_for_v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA DTS updates for v5.12
- Add DTS file for eASIC N5X platform
- Use generic ngpios in GPIO entries
- Add PMU node for Arria10

* tag 'socfpga_dts_update_for_v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: arria10: add PMU node
  arm64: dts: n5x: Add support for Intel's eASIC N5X platform
  arm64: dts: socfpga: Use generic "ngpios" rather than "snps,nr-gpios"

Link: https://lore.kernel.org/r/20210120012334.25730-1-dinguyen@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f791f1a4 b82a2707

arch/arm/boot/dts/socfpga_arria10.dtsi

+11 −2
Original line number Diff line number Diff line
@@ -15,13 +15,13 @@ cpus { 
		#size-cells = <0>;

		enable-method = "altr,socfpga-a10-smp";



		cpu@0 {

		cpu0: cpu@0 {

			compatible = "arm,cortex-a9";

			device_type = "cpu";

			reg = <0>;

			next-level-cache = <&L2>;

		};

		cpu@1 {

		cpu1: cpu@1 {

			compatible = "arm,cortex-a9";

			device_type = "cpu";

			reg = <1>;
@@ -29,6 +29,15 @@ cpu@1 { 
		};

	};



	pmu: pmu@ff111000 {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&intc>;

		interrupts = <0 124 4>, <0 125 4>;

		interrupt-affinity = <&cpu0>, <&cpu1>;

		reg = <0xff111000 0x1000>,

		      <0xff113000 0x1000>;

	};



	intc: intc@ffffd000 {

		compatible = "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

arch/arm64/Kconfig.platforms

+5 −0
Original line number Diff line number Diff line
@@ -13,6 +13,11 @@ config ARCH_AGILEX 
	help

	  This enables support for Intel's Agilex SoCFPGA Family.



config ARCH_N5X

	bool "Intel's eASIC N5X SoCFPGA Family"

	help

	  This enables support for Intel's eASIC N5X SoCFPGA Family.



config ARCH_SUNXI

	bool "Allwinner sunxi 64-bit SoC Family"

	select ARCH_HAS_RESET_CONTROLLER

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -203,7 +203,7 @@ porta: gpio-controller@0 { 
				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <24>;

				ngpios = <24>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;
@@ -223,7 +223,7 @@ portb: gpio-controller@0 { 
				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <24>;

				ngpios = <24>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

arch/arm64/boot/dts/intel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -2,3 +2,4 @@ 
dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \

			     socfpga_agilex_socdk_nand.dtb

dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb

dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb

arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts

0 → 100644
+53 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier:     GPL-2.0

/*

 * Copyright (C) 2021, Intel Corporation

 */

#include "socfpga_agilex.dtsi"



/ {

	model = "eASIC N5X SoCDK";



	aliases {

		serial0 = &uart0;

		ethernet0 = &gmac0;

		ethernet1 = &gmac1;

		ethernet2 = &gmac2;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory {

		device_type = "memory";

		/* We expect the bootloader to fill in the reg */

		reg = <0 0 0 0>;

	};



	soc {

		clocks {

			osc1 {

				clock-frequency = <25000000>;

			};

		};

	};

};



&clkmgr {

	compatible = "intel,easic-n5x-clkmgr";

};



&mmc {

	status = "okay";

	cap-sd-highspeed;

	broken-cd;

	bus-width = <4>;

};



&uart0 {

	status = "okay";

};



&watchdog0 {

	status = "okay";

};