Commit 7b9eb6cf authored by Zoltan HERPAI's avatar Zoltan HERPAI Committed by Linus Walleij
Browse files

ARM: dts: ixp4xx: Add devicetree for Gateway 7001 



This adds a device tree for the Gateway 7001 AP, based on
Intel IXP422.

Cc: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: default avatarZoltan HERPAI <wigyori@uid0.hu>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 65248dde

arch/arm/boot/dts/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -269,7 +269,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ 
	intel-ixp42x-gateworks-gw2348.dtb \

	intel-ixp43x-gateworks-gw2358.dtb \

	intel-ixp42x-netgear-wg302v2.dtb \

	intel-ixp42x-arcom-vulcan.dtb

	intel-ixp42x-arcom-vulcan.dtb \

	intel-ixp42x-gateway-7001.dtb

dtb-$(CONFIG_ARCH_KEYSTONE) += \

	keystone-k2hk-evm.dtb \

	keystone-k2l-evm.dtb \

arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts

0 → 100644
+111 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: ISC

/*

 * Device Tree file for Gateway 7001 AP

 * Derived from boardfiles written by Imre Kaloz

 */



/dts-v1/;



#include "intel-ixp42x.dtsi"

#include <dt-bindings/input/input.h>



/ {

	model = "Gateway 7001 AP";

	compatible = "gateway,7001", "intel,ixp42x";

	#address-cells = <1>;

	#size-cells = <1>;



	memory@0 {

		/* 32 MB SDRAM */

		device_type = "memory";

		reg = <0x00000000 0x2000000>;

	};



	chosen {

		bootargs = "console=ttyS0,115200n8";

		stdout-path = "uart1:115200n8";

	};



	aliases {

		/* second UART is the primary console */

		serial0 = &uart1;

		serial1 = &uart0;

	};



	soc {

		bus@c4000000 {

			flash@0,0 {

				compatible = "intel,ixp4xx-flash", "cfi-flash";

				bank-width = <2>;

				/*

				 * 8 MB of flash

				 */

				reg = <0 0x00000000 0x800000>;



				/* Configure expansion bus to allow writes */

				intel,ixp4xx-eb-write-enable = <1>;



				partitions {

					compatible = "redboot-fis";

					/* Eraseblock at 0x7e0000 */

					fis-index-block = <0x3f>;

				};

			};

		};



		pci@c0000000 {

			status = "ok";



			/*

			 * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c)

			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ

			 * each handling all IRQs.

			 */

			interrupt-map =

			/* IDSEL 1 */

			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

			<0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */

			<0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */

			<0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */

			/* IDSEL 2 */

			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */

			<0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */

			<0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */

			<0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */

		};



		ethernet@c8009000 {

			status = "ok";

			queue-rx = <&qmgr 3>;

			queue-txready = <&qmgr 20>;

			phy-mode = "rgmii";

			phy-handle = <&phy1>;



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;



				phy1: ethernet-phy@1 {

					reg = <1>;

				};

			};

		};



		ethernet@c800a000 {

			status = "ok";

			queue-rx = <&qmgr 4>;

			queue-txready = <&qmgr 21>;

			phy-mode = "rgmii";

			phy-handle = <&phy2>;



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;



				phy2: ethernet-phy@2 {

					reg = <2>;

				};

			};

		};

	};

};