Commit 799b9eb0 authored by Dafna Hirschfeld's avatar Dafna Hirschfeld Committed by Greg Kroah-Hartman
Browse files

habanalabs: remove debugfs read/write callbacks 



The debugfs memory access now uses the callback 'access_dev_mem'
so there is no use of the callbacks
'debugfs_{read32,read64,write32,write6}'. Remove them.

Signed-off-by: default avatarDafna Hirschfeld <dhirschfeld@habana.ai>
Reviewed-by: default avatarOded Gabbay <ogabbay@kernel.org>
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 9248aa90

drivers/misc/habanalabs/common/habanalabs.h

+0 −12
Original line number Diff line number Diff line
@@ -1282,10 +1282,6 @@ struct fw_load_mgr { 
 * @update_eq_ci: update event queue CI.

 * @context_switch: called upon ASID context switch.

 * @restore_phase_topology: clear all SOBs amd MONs.

 * @debugfs_read32: debug interface for reading u32 from DRAM/SRAM/Host memory.

 * @debugfs_write32: debug interface for writing u32 to DRAM/SRAM/Host memory.

 * @debugfs_read64: debug interface for reading u64 from DRAM/SRAM/Host memory.

 * @debugfs_write64: debug interface for writing u64 to DRAM/SRAM/Host memory.

 * @debugfs_read_dma: debug interface for reading up to 2MB from the device's

 *                    internal memory via DMA engine.

 * @add_device_attr: add ASIC specific device attributes.
@@ -1409,14 +1405,6 @@ struct hl_asic_funcs { 
	void (*update_eq_ci)(struct hl_device *hdev, u32 val);

	int (*context_switch)(struct hl_device *hdev, u32 asid);

	void (*restore_phase_topology)(struct hl_device *hdev);

	int (*debugfs_read32)(struct hl_device *hdev, u64 addr,

				bool user_address, u32 *val);

	int (*debugfs_write32)(struct hl_device *hdev, u64 addr,

				bool user_address, u32 val);

	int (*debugfs_read64)(struct hl_device *hdev, u64 addr,

				bool user_address, u64 *val);

	int (*debugfs_write64)(struct hl_device *hdev, u64 addr,

				bool user_address, u64 val);

	int (*debugfs_read_dma)(struct hl_device *hdev, u64 addr, u32 size,

				void *blob_addr);

	void (*add_device_attr)(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,

drivers/misc/habanalabs/gaudi/gaudi.c

+0 −182
Original line number Diff line number Diff line
@@ -6104,184 +6104,6 @@ static void gaudi_restore_phase_topology(struct hl_device *hdev) 


}



static int gaudi_debugfs_read32(struct hl_device *hdev, u64 addr,

			bool user_address, u32 *val)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u64 hbm_bar_addr, host_phys_end;

	int rc = 0;



	host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;



	if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {



		*val = RREG32(addr - CFG_BASE);



	} else if ((addr >= SRAM_BASE_ADDR) && (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {



		*val = readl(hdev->pcie_bar[SRAM_BAR_ID] + (addr - SRAM_BASE_ADDR));



	} else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {



		u64 bar_base_addr = DRAM_PHYS_BASE + (addr & ~(prop->dram_pci_bar_size - 0x1ull));



		hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);



		if (hbm_bar_addr != U64_MAX) {

			*val = readl(hdev->pcie_bar[HBM_BAR_ID] + (addr - bar_base_addr));

			hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, hbm_bar_addr);

		}



		if (hbm_bar_addr == U64_MAX)

			rc = -EIO;



	} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&

			user_address && !iommu_present(&pci_bus_type)) {



		*val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);



	} else {

		rc = -EFAULT;

	}



	return rc;

}



static int gaudi_debugfs_write32(struct hl_device *hdev, u64 addr,

			bool user_address, u32 val)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u64 hbm_bar_addr, host_phys_end;

	int rc = 0;



	host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;



	if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {



		WREG32(addr - CFG_BASE, val);



	} else if ((addr >= SRAM_BASE_ADDR) && (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {



		writel(val, hdev->pcie_bar[SRAM_BAR_ID] + (addr - SRAM_BASE_ADDR));



	} else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {



		u64 bar_base_addr = DRAM_PHYS_BASE + (addr & ~(prop->dram_pci_bar_size - 0x1ull));



		hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);



		if (hbm_bar_addr != U64_MAX) {

			writel(val, hdev->pcie_bar[HBM_BAR_ID] + (addr - bar_base_addr));

			hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, hbm_bar_addr);

		}



		if (hbm_bar_addr == U64_MAX)

			rc = -EIO;



	} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&

			user_address && !iommu_present(&pci_bus_type)) {



		*(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;



	} else {

		rc = -EFAULT;

	}



	return rc;

}



static int gaudi_debugfs_read64(struct hl_device *hdev, u64 addr,

				bool user_address, u64 *val)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u64 hbm_bar_addr, host_phys_end;

	int rc = 0;



	host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;



	if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {



		u32 val_l = RREG32(addr - CFG_BASE);

		u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);



		*val = (((u64) val_h) << 32) | val_l;



	} else if ((addr >= SRAM_BASE_ADDR) &&

			(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {



		*val = readq(hdev->pcie_bar[SRAM_BAR_ID] + (addr - SRAM_BASE_ADDR));



	} else if (addr <= DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {



		u64 bar_base_addr = DRAM_PHYS_BASE + (addr & ~(prop->dram_pci_bar_size - 0x1ull));



		hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);



		if (hbm_bar_addr != U64_MAX) {

			*val = readq(hdev->pcie_bar[HBM_BAR_ID] + (addr - bar_base_addr));

			hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, hbm_bar_addr);

		}



		if (hbm_bar_addr == U64_MAX)

			rc = -EIO;



	} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&

			user_address && !iommu_present(&pci_bus_type)) {



		*val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);



	} else {

		rc = -EFAULT;

	}



	return rc;

}



static int gaudi_debugfs_write64(struct hl_device *hdev, u64 addr,

				bool user_address, u64 val)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u64 hbm_bar_addr, host_phys_end;

	int rc = 0;



	host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;



	if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {



		WREG32(addr - CFG_BASE, lower_32_bits(val));

		WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));



	} else if ((addr >= SRAM_BASE_ADDR) &&

			(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {



		writeq(val, hdev->pcie_bar[SRAM_BAR_ID] + (addr - SRAM_BASE_ADDR));



	} else if (addr <= DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {



		u64 bar_base_addr = DRAM_PHYS_BASE + (addr & ~(prop->dram_pci_bar_size - 0x1ull));



		hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);



		if (hbm_bar_addr != U64_MAX) {

			writeq(val, hdev->pcie_bar[HBM_BAR_ID] + (addr - bar_base_addr));

			hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, hbm_bar_addr);

		}



		if (hbm_bar_addr == U64_MAX)

			rc = -EIO;



	} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&

			user_address && !iommu_present(&pci_bus_type)) {



		*(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;



	} else {

		rc = -EFAULT;

	}



	return rc;

}



static int gaudi_dma_core_transfer(struct hl_device *hdev, int dma_id, u64 addr,

					u32 size_to_dma, dma_addr_t dma_addr)

{
@@ -9450,10 +9272,6 @@ static const struct hl_asic_funcs gaudi_funcs = { 
	.update_eq_ci = gaudi_update_eq_ci,

	.context_switch = gaudi_context_switch,

	.restore_phase_topology = gaudi_restore_phase_topology,

	.debugfs_read32 = gaudi_debugfs_read32,

	.debugfs_write32 = gaudi_debugfs_write32,

	.debugfs_read64 = gaudi_debugfs_read64,

	.debugfs_write64 = gaudi_debugfs_write64,

	.debugfs_read_dma = gaudi_debugfs_read_dma,

	.add_device_attr = gaudi_add_device_attr,

	.handle_eqe = gaudi_handle_eqe,

drivers/misc/habanalabs/goya/goya.c

+1 −222
Original line number Diff line number Diff line
@@ -4262,224 +4262,7 @@ static void goya_clear_sm_regs(struct hl_device *hdev) 
	i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);

}



/*

 * goya_debugfs_read32 - read a 32bit value from a given device or a host mapped

 *                       address.

 *

 * @hdev:	pointer to hl_device structure

 * @addr:	device or host mapped address

 * @val:	returned value

 *

 * In case of DDR address that is not mapped into the default aperture that

 * the DDR bar exposes, the function will configure the iATU so that the DDR

 * bar will be positioned at a base address that allows reading from the

 * required address. Configuring the iATU during normal operation can

 * lead to undefined behavior and therefore, should be done with extreme care

 *

 */

static int goya_debugfs_read32(struct hl_device *hdev, u64 addr,

			bool user_address, u32 *val)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u64 ddr_bar_addr, host_phys_end;

	int rc = 0;



	host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;



	if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {

		*val = RREG32(addr - CFG_BASE);



	} else if ((addr >= SRAM_BASE_ADDR) &&

			(addr < SRAM_BASE_ADDR + SRAM_SIZE)) {



		*val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +

				(addr - SRAM_BASE_ADDR));



	} else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {



		u64 bar_base_addr = DRAM_PHYS_BASE +

				(addr & ~(prop->dram_pci_bar_size - 0x1ull));



		ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);

		if (ddr_bar_addr != U64_MAX) {

			*val = readl(hdev->pcie_bar[DDR_BAR_ID] +

						(addr - bar_base_addr));



			ddr_bar_addr = goya_set_ddr_bar_base(hdev,

							ddr_bar_addr);

		}

		if (ddr_bar_addr == U64_MAX)

			rc = -EIO;



	} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&

			user_address && !iommu_present(&pci_bus_type)) {

		*val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);



	} else {

		rc = -EFAULT;

	}



	return rc;

}



/*

 * goya_debugfs_write32 - write a 32bit value to a given device or a host mapped

 *                        address.

 *

 * @hdev:	pointer to hl_device structure

 * @addr:	device or host mapped address

 * @val:	returned value

 *

 * In case of DDR address that is not mapped into the default aperture that

 * the DDR bar exposes, the function will configure the iATU so that the DDR

 * bar will be positioned at a base address that allows writing to the

 * required address. Configuring the iATU during normal operation can

 * lead to undefined behavior and therefore, should be done with extreme care

 *

 */

static int goya_debugfs_write32(struct hl_device *hdev, u64 addr,

			bool user_address, u32 val)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u64 ddr_bar_addr, host_phys_end;

	int rc = 0;



	host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;



	if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {

		WREG32(addr - CFG_BASE, val);



	} else if ((addr >= SRAM_BASE_ADDR) &&

			(addr < SRAM_BASE_ADDR + SRAM_SIZE)) {



		writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +

					(addr - SRAM_BASE_ADDR));



	} else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {



		u64 bar_base_addr = DRAM_PHYS_BASE +

				(addr & ~(prop->dram_pci_bar_size - 0x1ull));



		ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);

		if (ddr_bar_addr != U64_MAX) {

			writel(val, hdev->pcie_bar[DDR_BAR_ID] +

						(addr - bar_base_addr));



			ddr_bar_addr = goya_set_ddr_bar_base(hdev,

							ddr_bar_addr);

		}

		if (ddr_bar_addr == U64_MAX)

			rc = -EIO;



	} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&

			user_address && !iommu_present(&pci_bus_type)) {

		*(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;



	} else {

		rc = -EFAULT;

	}



	return rc;

}



static int goya_debugfs_read64(struct hl_device *hdev, u64 addr,

			bool user_address, u64 *val)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u64 ddr_bar_addr, host_phys_end;

	int rc = 0;



	host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;



	if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {

		u32 val_l = RREG32(addr - CFG_BASE);

		u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);



		*val = (((u64) val_h) << 32) | val_l;



	} else if ((addr >= SRAM_BASE_ADDR) &&

			(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {



		*val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +

				(addr - SRAM_BASE_ADDR));



	} else if (addr <=

		   DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {



		u64 bar_base_addr = DRAM_PHYS_BASE +

				(addr & ~(prop->dram_pci_bar_size - 0x1ull));



		ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);

		if (ddr_bar_addr != U64_MAX) {

			*val = readq(hdev->pcie_bar[DDR_BAR_ID] +

						(addr - bar_base_addr));



			ddr_bar_addr = goya_set_ddr_bar_base(hdev,

							ddr_bar_addr);

		}

		if (ddr_bar_addr == U64_MAX)

			rc = -EIO;



	} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&

			user_address && !iommu_present(&pci_bus_type)) {

		*val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);



	} else {

		rc = -EFAULT;

	}



	return rc;

}



static int goya_debugfs_write64(struct hl_device *hdev, u64 addr,

				bool user_address, u64 val)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u64 ddr_bar_addr, host_phys_end;

	int rc = 0;



	host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;



	if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {

		WREG32(addr - CFG_BASE, lower_32_bits(val));

		WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));



	} else if ((addr >= SRAM_BASE_ADDR) &&

			(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {



		writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +

					(addr - SRAM_BASE_ADDR));



	} else if (addr <=

		   DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {



		u64 bar_base_addr = DRAM_PHYS_BASE +

				(addr & ~(prop->dram_pci_bar_size - 0x1ull));



		ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);

		if (ddr_bar_addr != U64_MAX) {

			writeq(val, hdev->pcie_bar[DDR_BAR_ID] +

						(addr - bar_base_addr));



			ddr_bar_addr = goya_set_ddr_bar_base(hdev,

							ddr_bar_addr);

		}

		if (ddr_bar_addr == U64_MAX)

			rc = -EIO;



	} else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&

			user_address && !iommu_present(&pci_bus_type)) {

		*(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;



	} else {

		rc = -EFAULT;

	}



	return rc;

}



static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,

				void *blob_addr)

static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr)

{

	dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");

	return -EPERM;
@@ -5725,10 +5508,6 @@ static const struct hl_asic_funcs goya_funcs = { 
	.update_eq_ci = goya_update_eq_ci,

	.context_switch = goya_context_switch,

	.restore_phase_topology = goya_restore_phase_topology,

	.debugfs_read32 = goya_debugfs_read32,

	.debugfs_write32 = goya_debugfs_write32,

	.debugfs_read64 = goya_debugfs_read64,

	.debugfs_write64 = goya_debugfs_write64,

	.debugfs_read_dma = goya_debugfs_read_dma,

	.add_device_attr = goya_add_device_attr,

	.handle_eqe = goya_handle_eqe,