Commit 785908cf authored by Jaehyun Chung's avatar Jaehyun Chung Committed by Alex Deucher
Browse files

drm/amd/display: OTC underflow fix 



[Why] Underflow occurs on some display setups(repro'd on 3x4K HDR) on boot,
mode set, and hot-plugs with. Underflow occurs because mem clk
is not set high after disabling pstate switching. This behaviour occurs
because some calculations assumed displays were synchronized.

[How] Add a condition to check if timing sync is disabled so that
synchronized vblank can be set to false.

Signed-off-by: default avatarJaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 11963006

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1759,7 +1759,7 @@ int dcn20_populate_dml_pipes_from_context( 
			pipe_cnt = i;

			continue;

		}

		if (!resource_are_streams_timing_synchronizable(

		if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(

				res_ctx->pipe_ctx[pipe_cnt].stream,

				res_ctx->pipe_ctx[i].stream)) {

			synchronized_vblank = false;