Commit 73feb5c0 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
Browse files

Blackfin arch: fix bugs and unify BFIN_KERNEL_CLOCK option 



 - remove duplicated code and headers
 - add option allowing arbitrary SDRAM/DDR Timing parameters.
 - mark automatically calculated timings as EXPERIMENTAL
 - fix comment header block

Related to BUGs:
 - kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on.
 - kernel does not boot if re-program clocks

[ Mike Frysinger <vapier.adi@gmail.com>
 - fix comment header
 - mark do_sync static
 - document the DMA shutdown
 - simplify SIC_IWR handling
 - fix ANOMALY_05000265 handling to work as intended ]

Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent c97618d3

arch/blackfin/Kconfig

+57 −2
Original line number Diff line number Diff line
@@ -473,6 +473,61 @@ config MEM_MT46V32M16_5B 
	bool "MT46V32M16_5B"

endchoice



choice

	prompt "DDR/SDRAM Timing"

	depends on BFIN_KERNEL_CLOCK

	default BFIN_KERNEL_CLOCK_MEMINIT_CALC

	help

	  This option allows you to specify Blackfin SDRAM/DDR Timing parameters

	  The calculated SDRAM timing parameters may not be 100%

	  accurate - This option is therefore marked experimental.



config BFIN_KERNEL_CLOCK_MEMINIT_CALC

	bool "Calculate Timings (EXPERIMENTAL)"

	depends on EXPERIMENTAL



config BFIN_KERNEL_CLOCK_MEMINIT_SPEC

	bool "Provide accurate Timings based on target SCLK"

	help

	  Please consult the Blackfin Hardware Reference Manuals as well

	  as the memory device datasheet.

	  http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram

endchoice



menu "Memory Init Control"

	depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC



config MEM_DDRCTL0

	depends on BF54x

	hex "DDRCTL0"

	default 0x0



config MEM_DDRCTL1

	depends on BF54x

	hex "DDRCTL1"

	default 0x0



config MEM_DDRCTL2

	depends on BF54x

	hex "DDRCTL2"

	default 0x0



config MEM_EBIU_DDRQUE

	depends on BF54x

	hex "DDRQUE"

	default 0x0



config MEM_SDRRC

	depends on !BF54x

	hex "SDRRC"

	default 0x0



config MEM_SDGCTL

	depends on !BF54x

	hex "SDGCTL"

	default 0x0

endmenu



config MAX_MEM_SIZE

	int "Max SDRAM Memory Size in MBytes"

	depends on !MPU

arch/blackfin/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y) 
CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')

CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__



head-y   := arch/$(ARCH)/mach-$(MACHINE)/head.o arch/$(ARCH)/kernel/init_task.o

head-y   := arch/$(ARCH)/kernel/init_task.o



core-y   += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/

arch/blackfin/mach-bf518/include/mach/mem_init.h→arch/blackfin/include/asm/mem_init.h

+107 −55
Original line number Diff line number Diff line 
/*

 * File:         include/asm-blackfin/mach-bf518/mem_init.h

 * Based on:

 * Author:

 * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory

 *

 * Created:

 * Description:

 * Copyright 2004-2008 Analog Devices Inc.

 *

 * Rev:

 *

 * Modified:

 *               Copyright 2004-2007 Analog Devices Inc.

 *

 * Bugs:         Enter bugs at http://blackfin.uclinux.org/

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2, or (at your option)

 * any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; see the file COPYING.

 * If not, write to the Free Software Foundation,

 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

 * Licensed under the GPL-2 or later.

 */



#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)

#if defined(EBIU_SDGCTL)

#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \

    defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \

    defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \

    defined(CONFIG_MEM_GENERIC_BOARD) || \

    defined(CONFIG_MEM_MT48LC32M8A2_75) || \

    defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \

    defined(CONFIG_MEM_MT48LC32M16A2TG_75)

#if (CONFIG_SCLK_HZ > 119402985)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2
@@ -104,53 +88,113 @@ 
#endif

#endif



#if (CONFIG_MEM_MT48LC16M16A2TG_75)

  /*SDRAM INFORMATION: */

#define SDRAM_Tref  64		/* Refresh period in milliseconds   */

#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */

#define SDRAM_CL    CL_3

#endif



#if (CONFIG_MEM_MT48LC16M8A2TG_75)

#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \

    defined(CONFIG_MEM_MT48LC8M32B2B5_7)

  /*SDRAM INFORMATION: */

#define SDRAM_Tref  64		/* Refresh period in milliseconds   */

#define SDRAM_NRA   4096	/* Number of row addresses in SDRAM */

#define SDRAM_CL    CL_3

#endif



#if (CONFIG_MEM_MT48LC32M8A2_75)

#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \

    defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \

    defined(CONFIG_MEM_GENERIC_BOARD) || \

    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \

    defined(CONFIG_MEM_MT48LC16M16A2TG_75)

  /*SDRAM INFORMATION: */

#define SDRAM_Tref  64		/* Refresh period in milliseconds   */

#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */

#define SDRAM_CL    CL_3

#endif



#if (CONFIG_MEM_MT48LC64M4A2FB_7E)

  /*SDRAM INFORMATION: */

#define SDRAM_Tref  64		/* Refresh period in milliseconds   */

#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */

#define SDRAM_CL    CL_3



#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC

/* Equation from section 17 (p17-46) of BF533 HRM */

#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)



/* Enable SCLK Out */

#define mem_SDGCTL        (0x80000000 | SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)

#else

#define mem_SDRRC 	CONFIG_MEM_SDRRC

#define mem_SDGCTL	CONFIG_MEM_SDGCTL

#endif

#endif



#if (CONFIG_MEM_GENERIC_BOARD)

  /*SDRAM INFORMATION: Modify this for your board */

#define SDRAM_Tref  64		/* Refresh period in milliseconds   */

#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */

#define SDRAM_CL    CL_3



#if defined(EBIU_DDRCTL0)

#define MIN_DDR_SCLK(x)	(x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)

#define MAX_DDR_SCLK(x)	(x*(CONFIG_SCLK_HZ/1000/1000)/1000)

#define DDR_CLK_HZ(x)	(1000*1000*1000/x)



#if defined(CONFIG_MEM_MT46V32M16_6T)

#define DDR_SIZE	DEVSZ_512

#define DDR_WIDTH	DEVWD_16

#define DDR_MAX_tCK	13



#define DDR_tRC		DDR_TRC(MIN_DDR_SCLK(60))

#define DDR_tRAS	DDR_TRAS(MIN_DDR_SCLK(42))

#define DDR_tRP		DDR_TRP(MIN_DDR_SCLK(15))

#define DDR_tRFC	DDR_TRFC(MIN_DDR_SCLK(72))

#define DDR_tREFI	DDR_TREFI(MAX_DDR_SCLK(7800))



#define DDR_tRCD	DDR_TRCD(MIN_DDR_SCLK(15))

#define DDR_tWTR	DDR_TWTR(1)

#define DDR_tMRD	DDR_TMRD(MIN_DDR_SCLK(12))

#define DDR_tWR		DDR_TWR(MIN_DDR_SCLK(15))

#endif



#if (CONFIG_MEM_MT48LC32M16A2TG_75)

  /*SDRAM INFORMATION: */

#define SDRAM_Tref  64		/* Refresh period in milliseconds   */

#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */

#define SDRAM_CL    CL_3

#if defined(CONFIG_MEM_MT46V32M16_5B)

#define DDR_SIZE	DEVSZ_512

#define DDR_WIDTH	DEVWD_16

#define DDR_MAX_tCK	13



#define DDR_tRC		DDR_TRC(MIN_DDR_SCLK(55))

#define DDR_tRAS	DDR_TRAS(MIN_DDR_SCLK(40))

#define DDR_tRP		DDR_TRP(MIN_DDR_SCLK(15))

#define DDR_tRFC	DDR_TRFC(MIN_DDR_SCLK(70))

#define DDR_tREFI	DDR_TREFI(MAX_DDR_SCLK(7800))



#define DDR_tRCD	DDR_TRCD(MIN_DDR_SCLK(15))

#define DDR_tWTR	DDR_TWTR(2)

#define DDR_tMRD	DDR_TMRD(MIN_DDR_SCLK(10))

#define DDR_tWR		DDR_TWR(MIN_DDR_SCLK(15))

#endif



/* Equation from section 17 (p17-46) of BF533 HRM */

#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)

#if defined(CONFIG_MEM_GENERIC_BOARD)

#define DDR_SIZE	DEVSZ_512

#define DDR_WIDTH	DEVWD_16

#define DDR_MAX_tCK	13



/* Enable SCLK Out */

#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)

#define DDR_tRCD	DDR_TRCD(3)

#define DDR_tWTR	DDR_TWTR(2)

#define DDR_tWR		DDR_TWR(2)

#define DDR_tMRD	DDR_TMRD(2)

#define DDR_tRP		DDR_TRP(3)

#define DDR_tRAS	DDR_TRAS(7)

#define DDR_tRC		DDR_TRC(10)

#define DDR_tRFC	DDR_TRFC(12)

#define DDR_tREFI	DDR_TREFI(1288)

#endif



#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))

# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."

#elif(CONFIG_SCLK_HZ <= 133333333)

# define	DDR_CL		CL_2

#else

# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."

#endif



#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC

#define mem_DDRCTL0	(DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)

#define mem_DDRCTL1	(DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \

			| DDR_tMRD | DDR_tWR | DDR_tRCD)

#define mem_DDRCTL2	DDR_CL

#else

#define mem_DDRCTL0	CONFIG_MEM_DDRCTL0

#define mem_DDRCTL1	CONFIG_MEM_DDRCTL1

#define mem_DDRCTL2	CONFIG_MEM_DDRCTL2

#endif

#endif



#if defined CONFIG_CLKIN_HALF

#define CLKIN_HALF       1
@@ -165,6 +209,13 @@ 
#endif



/***************************************Currently Not Being Used *********************************/



#if defined(CONFIG_FLASH_SPEED_BWAT) && \

defined(CONFIG_FLASH_SPEED_BRAT) && \

defined(CONFIG_FLASH_SPEED_BHT) && \

defined(CONFIG_FLASH_SPEED_BST) && \

defined(CONFIG_FLASH_SPEED_BTT)



#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1

#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1

#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
@@ -308,3 +359,4 @@ 
#define flash_EBIU_AMBCTL0  \

	(flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \

	 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)

#endif

arch/blackfin/mach-bf518/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -2,6 +2,4 @@ 
# arch/blackfin/mach-bf518/Makefile

#



extra-y := head.o



obj-y := ints-priority.o dma.o

arch/blackfin/mach-bf518/head.S

deleted100644 → 0
+0 −146
Original line number Diff line number Diff line 
/*

 * File:         arch/blackfin/mach-bf518/head.S

 * Based on:     arch/blackfin/mach-bf527/head.S

 * Author:       Bryan Wu <cooloney@kernel.org>

 *

 * Created:      2008

 * Description:  Startup code for Blackfin BF51x

 *

 * Modified:

 *               Copyright 2004-2008 Analog Devices Inc.

 *

 * Bugs:         Enter bugs at http://blackfin.uclinux.org/

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, see the file COPYING, or write

 * to the Free Software Foundation, Inc.,

 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */



#include <linux/linkage.h>

#include <linux/init.h>

#include <asm/blackfin.h>

#ifdef CONFIG_BFIN_KERNEL_CLOCK

#include <asm/mach-common/clocks.h>

#include <asm/mach/mem_init.h>

#endif



.section .l1.text

#ifdef CONFIG_BFIN_KERNEL_CLOCK

ENTRY(_start_dma_code)



	/* Enable PHY CLK buffer output */

	p0.h = hi(VR_CTL);

	p0.l = lo(VR_CTL);

	r0.l = w[p0];

	bitset(r0, 14);

	w[p0] = r0.l;

	ssync;



	p0.h = hi(SIC_IWR0);

	p0.l = lo(SIC_IWR0);

	r0.l = 0x1;

	r0.h = 0x0;

	[p0] = r0;

	ssync;



	/*

	 *  Set PLL_CTL

	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors

	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK

	 *   - [7]     = output delay (add 200ps of delay to mem signals)

	 *   - [6]     = input delay (add 200ps of input delay to mem signals)

	 *   - [5]     = PDWN      : 1=All Clocks off

	 *   - [3]     = STOPCK    : 1=Core Clock off

	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL

	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL

	 *   all other bits set to zero

	 */



	p0.h = hi(PLL_LOCKCNT);

	p0.l = lo(PLL_LOCKCNT);

	r0 = 0x300(Z);

	w[p0] = r0.l;

	ssync;



	P2.H = hi(EBIU_SDGCTL);

	P2.L = lo(EBIU_SDGCTL);

	R0 = [P2];

	BITSET (R0, 24);

	[P2] = R0;

	ssync;



	r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */

	r0 = r0 << 9;                    /* Shift it over,                  */

	r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/

	r0 = r1 | r0;

	r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */

	r1 = r1 << 8;                    /* Shift it over                   */

	r0 = r1 | r0;                    /* add them all together           */

#ifdef ANOMALY_05000265

	BITSET(r0, 15);                  /* Add 250 mV of hysteresis to SPORT input pins */

#endif



	p0.h = hi(PLL_CTL);

	p0.l = lo(PLL_CTL);              /* Load the address                */

	cli r2;                          /* Disable interrupts              */

	ssync;

	w[p0] = r0.l;                    /* Set the value                   */

	idle;                            /* Wait for the PLL to stablize    */

	sti r2;                          /* Enable interrupts               */



.Lcheck_again:

	p0.h = hi(PLL_STAT);

	p0.l = lo(PLL_STAT);

	R0 = W[P0](Z);

	CC = BITTST(R0,5);

	if ! CC jump .Lcheck_again;



	/* Configure SCLK & CCLK Dividers */

	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);

	p0.h = hi(PLL_DIV);

	p0.l = lo(PLL_DIV);

	w[p0] = r0.l;

	ssync;



	p0.l = lo(EBIU_SDRRC);

	p0.h = hi(EBIU_SDRRC);

	r0 = mem_SDRRC;

	w[p0] = r0.l;

	ssync;



	P2.H = hi(EBIU_SDGCTL);

	P2.L = lo(EBIU_SDGCTL);

	R0 = [P2];

	BITCLR (R0, 24);

	p0.h = hi(EBIU_SDSTAT);

	p0.l = lo(EBIU_SDSTAT);

	r2.l = w[p0];

	cc = bittst(r2,3);

	if !cc jump .Lskip;

	NOP;

	BITSET (R0, 23);

.Lskip:

	[P2] = R0;

	SSYNC;



	R0.L = lo(mem_SDGCTL);

	R0.H = hi(mem_SDGCTL);

	R1 = [p2];

	R1 = R1 | R0;

	[P2] = R1;

	SSYNC;



	RTS;

ENDPROC(_start_dma_code)

#endif /* CONFIG_BFIN_KERNEL_CLOCK */