Commit 7144d3cf authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: separate out wm change request dcn workaround 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 69d6bb17

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c

+6 −5
Original line number Diff line number Diff line
@@ -190,6 +190,12 @@ static uint32_t convert_and_clamp( 
}





void hubbub1_wm_change_req_wa(struct hubbub *hubbub)

{

	REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,

			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);

}



void hubbub1_program_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,
@@ -203,8 +209,6 @@ void hubbub1_program_watermarks( 
	 */

	uint32_t prog_wm_value;



	REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,

			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);



	/* Repeat for water mark set A, B, C and D. */

	/* clock state A */
@@ -459,9 +463,6 @@ void hubbub1_program_watermarks( 
			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);

	}



	REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,

			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);



	REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,

			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);

	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

+2 −0
Original line number Diff line number Diff line
@@ -195,6 +195,8 @@ void hubbub1_update_dchub( 
bool hubbub1_verify_allow_pstate_change_high(

	struct hubbub *hubbub);



void hubbub1_wm_change_req_wa(struct hubbub *hubbub);



void hubbub1_program_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −0
Original line number Diff line number Diff line
@@ -2305,6 +2305,9 @@ static void dcn10_apply_ctx_for_surface( 
		hubbub1_program_watermarks(dc->res_pool->hubbub,

				&context->bw.dcn.watermarks, ref_clk_mhz, true);



		if (dc->hwseq->wa.DEGVIDCN10_254)

			hubbub1_wm_change_req_wa(dc->res_pool->hubbub);



		if (dc->debug.sanity_checks) {

			/* pstate stuck check after watermark update */

			dcn10_verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -743,6 +743,7 @@ static struct dce_hwseq *dcn10_hwseq_create( 
		hws->masks = &hwseq_mask;

		hws->wa.DEGVIDCN10_253 = true;

		hws->wa.false_optc_underflow = true;

		hws->wa.DEGVIDCN10_254 = true;

	}

	return hws;

}

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ struct dce_hwseq_wa { 
	bool blnd_crtc_trigger;

	bool DEGVIDCN10_253;

	bool false_optc_underflow;

	bool DEGVIDCN10_254;

};



struct hwseq_wa_state {