Commit 6fa91f64 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Refresh bonnell events 

Update the bonnell events using the new tooling from:

  https://github.com/intel/perfmon



The events are unchanged but unused json values are removed and
implicit umasks of 0 are dropped. This increases consistency across
the json files.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215064755.1620246-5-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent a5abef62

tools/perf/pmu-events/arch/x86/bonnell/cache.json

+0 −93
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "L1 Data Cacheable reads and writes",

        "Counter": "0,1",

        "EventCode": "0x40",

        "EventName": "L1D_CACHE.ALL_CACHE_REF",

        "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@ 
    },

    {

        "BriefDescription": "L1 Data reads and writes",

        "Counter": "0,1",

        "EventCode": "0x40",

        "EventName": "L1D_CACHE.ALL_REF",

        "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@ 
    },

    {

        "BriefDescription": "Modified cache lines evicted from the L1 data cache",

        "Counter": "0,1",

        "EventCode": "0x40",

        "EventName": "L1D_CACHE.EVICT",

        "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@ 
    },

    {

        "BriefDescription": "L1 Cacheable Data Reads",

        "Counter": "0,1",

        "EventCode": "0x40",

        "EventName": "L1D_CACHE.LD",

        "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@ 
    },

    {

        "BriefDescription": "L1 Data line replacements",

        "Counter": "0,1",

        "EventCode": "0x40",

        "EventName": "L1D_CACHE.REPL",

        "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@ 
    },

    {

        "BriefDescription": "Modified cache lines allocated in the L1 data cache",

        "Counter": "0,1",

        "EventCode": "0x40",

        "EventName": "L1D_CACHE.REPLM",

        "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@ 
    },

    {

        "BriefDescription": "L1 Cacheable Data Writes",

        "Counter": "0,1",

        "EventCode": "0x40",

        "EventName": "L1D_CACHE.ST",

        "SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@ 
    },

    {

        "BriefDescription": "Cycles L2 address bus is in use.",

        "Counter": "0,1",

        "EventCode": "0x21",

        "EventName": "L2_ADS.SELF",

        "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@ 
    },

    {

        "BriefDescription": "All data requests from the L1 data cache",

        "Counter": "0,1",

        "EventCode": "0x2C",

        "EventName": "L2_DATA_RQSTS.SELF.E_STATE",

        "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@ 
    },

    {

        "BriefDescription": "All data requests from the L1 data cache",

        "Counter": "0,1",

        "EventCode": "0x2C",

        "EventName": "L2_DATA_RQSTS.SELF.I_STATE",

        "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@ 
    },

    {

        "BriefDescription": "All data requests from the L1 data cache",

        "Counter": "0,1",

        "EventCode": "0x2C",

        "EventName": "L2_DATA_RQSTS.SELF.MESI",

        "SampleAfterValue": "200000",
@@ -89,7 +78,6 @@ 
    },

    {

        "BriefDescription": "All data requests from the L1 data cache",

        "Counter": "0,1",

        "EventCode": "0x2C",

        "EventName": "L2_DATA_RQSTS.SELF.M_STATE",

        "SampleAfterValue": "200000",
@@ -97,7 +85,6 @@ 
    },

    {

        "BriefDescription": "All data requests from the L1 data cache",

        "Counter": "0,1",

        "EventCode": "0x2C",

        "EventName": "L2_DATA_RQSTS.SELF.S_STATE",

        "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@ 
    },

    {

        "BriefDescription": "Cycles the L2 cache data bus is busy.",

        "Counter": "0,1",

        "EventCode": "0x22",

        "EventName": "L2_DBUS_BUSY.SELF",

        "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@ 
    },

    {

        "BriefDescription": "Cycles the L2 transfers data to the core.",

        "Counter": "0,1",

        "EventCode": "0x23",

        "EventName": "L2_DBUS_BUSY_RD.SELF",

        "SampleAfterValue": "200000",
@@ -121,7 +106,6 @@ 
    },

    {

        "BriefDescription": "L2 cacheable instruction fetch requests",

        "Counter": "0,1",

        "EventCode": "0x28",

        "EventName": "L2_IFETCH.SELF.E_STATE",

        "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@ 
    },

    {

        "BriefDescription": "L2 cacheable instruction fetch requests",

        "Counter": "0,1",

        "EventCode": "0x28",

        "EventName": "L2_IFETCH.SELF.I_STATE",

        "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@ 
    },

    {

        "BriefDescription": "L2 cacheable instruction fetch requests",

        "Counter": "0,1",

        "EventCode": "0x28",

        "EventName": "L2_IFETCH.SELF.MESI",

        "SampleAfterValue": "200000",
@@ -145,7 +127,6 @@ 
    },

    {

        "BriefDescription": "L2 cacheable instruction fetch requests",

        "Counter": "0,1",

        "EventCode": "0x28",

        "EventName": "L2_IFETCH.SELF.M_STATE",

        "SampleAfterValue": "200000",
@@ -153,7 +134,6 @@ 
    },

    {

        "BriefDescription": "L2 cacheable instruction fetch requests",

        "Counter": "0,1",

        "EventCode": "0x28",

        "EventName": "L2_IFETCH.SELF.S_STATE",

        "SampleAfterValue": "200000",
@@ -161,7 +141,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.ANY.E_STATE",

        "SampleAfterValue": "200000",
@@ -169,7 +148,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.ANY.I_STATE",

        "SampleAfterValue": "200000",
@@ -177,7 +155,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.ANY.MESI",

        "SampleAfterValue": "200000",
@@ -185,7 +162,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.ANY.M_STATE",

        "SampleAfterValue": "200000",
@@ -193,7 +169,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.ANY.S_STATE",

        "SampleAfterValue": "200000",
@@ -201,7 +176,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.DEMAND.E_STATE",

        "SampleAfterValue": "200000",
@@ -209,7 +183,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.DEMAND.I_STATE",

        "SampleAfterValue": "200000",
@@ -217,7 +190,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.DEMAND.MESI",

        "SampleAfterValue": "200000",
@@ -225,7 +197,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.DEMAND.M_STATE",

        "SampleAfterValue": "200000",
@@ -233,7 +204,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.DEMAND.S_STATE",

        "SampleAfterValue": "200000",
@@ -241,7 +211,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.PREFETCH.E_STATE",

        "SampleAfterValue": "200000",
@@ -249,7 +218,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.PREFETCH.I_STATE",

        "SampleAfterValue": "200000",
@@ -257,7 +225,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.PREFETCH.MESI",

        "SampleAfterValue": "200000",
@@ -265,7 +232,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.PREFETCH.M_STATE",

        "SampleAfterValue": "200000",
@@ -273,7 +239,6 @@ 
    },

    {

        "BriefDescription": "L2 cache reads",

        "Counter": "0,1",

        "EventCode": "0x29",

        "EventName": "L2_LD.SELF.PREFETCH.S_STATE",

        "SampleAfterValue": "200000",
@@ -281,7 +246,6 @@ 
    },

    {

        "BriefDescription": "All read requests from L1 instruction and data caches",

        "Counter": "0,1",

        "EventCode": "0x2D",

        "EventName": "L2_LD_IFETCH.SELF.E_STATE",

        "SampleAfterValue": "200000",
@@ -289,7 +253,6 @@ 
    },

    {

        "BriefDescription": "All read requests from L1 instruction and data caches",

        "Counter": "0,1",

        "EventCode": "0x2D",

        "EventName": "L2_LD_IFETCH.SELF.I_STATE",

        "SampleAfterValue": "200000",
@@ -297,7 +260,6 @@ 
    },

    {

        "BriefDescription": "All read requests from L1 instruction and data caches",

        "Counter": "0,1",

        "EventCode": "0x2D",

        "EventName": "L2_LD_IFETCH.SELF.MESI",

        "SampleAfterValue": "200000",
@@ -305,7 +267,6 @@ 
    },

    {

        "BriefDescription": "All read requests from L1 instruction and data caches",

        "Counter": "0,1",

        "EventCode": "0x2D",

        "EventName": "L2_LD_IFETCH.SELF.M_STATE",

        "SampleAfterValue": "200000",
@@ -313,7 +274,6 @@ 
    },

    {

        "BriefDescription": "All read requests from L1 instruction and data caches",

        "Counter": "0,1",

        "EventCode": "0x2D",

        "EventName": "L2_LD_IFETCH.SELF.S_STATE",

        "SampleAfterValue": "200000",
@@ -321,7 +281,6 @@ 
    },

    {

        "BriefDescription": "L2 cache misses.",

        "Counter": "0,1",

        "EventCode": "0x24",

        "EventName": "L2_LINES_IN.SELF.ANY",

        "SampleAfterValue": "200000",
@@ -329,7 +288,6 @@ 
    },

    {

        "BriefDescription": "L2 cache misses.",

        "Counter": "0,1",

        "EventCode": "0x24",

        "EventName": "L2_LINES_IN.SELF.DEMAND",

        "SampleAfterValue": "200000",
@@ -337,7 +295,6 @@ 
    },

    {

        "BriefDescription": "L2 cache misses.",

        "Counter": "0,1",

        "EventCode": "0x24",

        "EventName": "L2_LINES_IN.SELF.PREFETCH",

        "SampleAfterValue": "200000",
@@ -345,7 +302,6 @@ 
    },

    {

        "BriefDescription": "L2 cache lines evicted.",

        "Counter": "0,1",

        "EventCode": "0x26",

        "EventName": "L2_LINES_OUT.SELF.ANY",

        "SampleAfterValue": "200000",
@@ -353,7 +309,6 @@ 
    },

    {

        "BriefDescription": "L2 cache lines evicted.",

        "Counter": "0,1",

        "EventCode": "0x26",

        "EventName": "L2_LINES_OUT.SELF.DEMAND",

        "SampleAfterValue": "200000",
@@ -361,7 +316,6 @@ 
    },

    {

        "BriefDescription": "L2 cache lines evicted.",

        "Counter": "0,1",

        "EventCode": "0x26",

        "EventName": "L2_LINES_OUT.SELF.PREFETCH",

        "SampleAfterValue": "200000",
@@ -369,7 +323,6 @@ 
    },

    {

        "BriefDescription": "L2 locked accesses",

        "Counter": "0,1",

        "EventCode": "0x2B",

        "EventName": "L2_LOCK.SELF.E_STATE",

        "SampleAfterValue": "200000",
@@ -377,7 +330,6 @@ 
    },

    {

        "BriefDescription": "L2 locked accesses",

        "Counter": "0,1",

        "EventCode": "0x2B",

        "EventName": "L2_LOCK.SELF.I_STATE",

        "SampleAfterValue": "200000",
@@ -385,7 +337,6 @@ 
    },

    {

        "BriefDescription": "L2 locked accesses",

        "Counter": "0,1",

        "EventCode": "0x2B",

        "EventName": "L2_LOCK.SELF.MESI",

        "SampleAfterValue": "200000",
@@ -393,7 +344,6 @@ 
    },

    {

        "BriefDescription": "L2 locked accesses",

        "Counter": "0,1",

        "EventCode": "0x2B",

        "EventName": "L2_LOCK.SELF.M_STATE",

        "SampleAfterValue": "200000",
@@ -401,7 +351,6 @@ 
    },

    {

        "BriefDescription": "L2 locked accesses",

        "Counter": "0,1",

        "EventCode": "0x2B",

        "EventName": "L2_LOCK.SELF.S_STATE",

        "SampleAfterValue": "200000",
@@ -409,7 +358,6 @@ 
    },

    {

        "BriefDescription": "L2 cache line modifications.",

        "Counter": "0,1",

        "EventCode": "0x25",

        "EventName": "L2_M_LINES_IN.SELF",

        "SampleAfterValue": "200000",
@@ -417,7 +365,6 @@ 
    },

    {

        "BriefDescription": "Modified lines evicted from the L2 cache",

        "Counter": "0,1",

        "EventCode": "0x27",

        "EventName": "L2_M_LINES_OUT.SELF.ANY",

        "SampleAfterValue": "200000",
@@ -425,7 +372,6 @@ 
    },

    {

        "BriefDescription": "Modified lines evicted from the L2 cache",

        "Counter": "0,1",

        "EventCode": "0x27",

        "EventName": "L2_M_LINES_OUT.SELF.DEMAND",

        "SampleAfterValue": "200000",
@@ -433,7 +379,6 @@ 
    },

    {

        "BriefDescription": "Modified lines evicted from the L2 cache",

        "Counter": "0,1",

        "EventCode": "0x27",

        "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",

        "SampleAfterValue": "200000",
@@ -441,7 +386,6 @@ 
    },

    {

        "BriefDescription": "Cycles no L2 cache requests are pending",

        "Counter": "0,1",

        "EventCode": "0x32",

        "EventName": "L2_NO_REQ.SELF",

        "SampleAfterValue": "200000",
@@ -449,7 +393,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",

        "SampleAfterValue": "200000",
@@ -457,7 +400,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",

        "SampleAfterValue": "200000",
@@ -465,7 +407,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",

        "SampleAfterValue": "200000",
@@ -473,7 +414,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",

        "SampleAfterValue": "200000",
@@ -481,7 +421,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",

        "SampleAfterValue": "200000",
@@ -489,7 +428,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",

        "SampleAfterValue": "200000",
@@ -497,7 +435,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",

        "SampleAfterValue": "200000",
@@ -505,7 +442,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",

        "SampleAfterValue": "200000",
@@ -513,7 +449,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",

        "SampleAfterValue": "200000",
@@ -521,7 +456,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",

        "SampleAfterValue": "200000",
@@ -529,7 +463,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",

        "SampleAfterValue": "200000",
@@ -537,7 +470,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",

        "SampleAfterValue": "200000",
@@ -545,7 +477,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",

        "SampleAfterValue": "200000",
@@ -553,7 +484,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",

        "SampleAfterValue": "200000",
@@ -561,7 +491,6 @@ 
    },

    {

        "BriefDescription": "Rejected L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x30",

        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",

        "SampleAfterValue": "200000",
@@ -569,7 +498,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.ANY.E_STATE",

        "SampleAfterValue": "200000",
@@ -577,7 +505,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.ANY.I_STATE",

        "SampleAfterValue": "200000",
@@ -585,7 +512,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.ANY.MESI",

        "SampleAfterValue": "200000",
@@ -593,7 +519,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.ANY.M_STATE",

        "SampleAfterValue": "200000",
@@ -601,7 +526,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.ANY.S_STATE",

        "SampleAfterValue": "200000",
@@ -609,7 +533,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",

        "SampleAfterValue": "200000",
@@ -617,7 +540,6 @@ 
    },

    {

        "BriefDescription": "L2 cache demand requests from this core that missed the L2",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",

        "SampleAfterValue": "200000",
@@ -625,7 +547,6 @@ 
    },

    {

        "BriefDescription": "L2 cache demand requests from this core",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.DEMAND.MESI",

        "SampleAfterValue": "200000",
@@ -633,7 +554,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",

        "SampleAfterValue": "200000",
@@ -641,7 +561,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",

        "SampleAfterValue": "200000",
@@ -649,7 +568,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",

        "SampleAfterValue": "200000",
@@ -657,7 +575,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",

        "SampleAfterValue": "200000",
@@ -665,7 +582,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",

        "SampleAfterValue": "200000",
@@ -673,7 +589,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",

        "SampleAfterValue": "200000",
@@ -681,7 +596,6 @@ 
    },

    {

        "BriefDescription": "L2 cache requests",

        "Counter": "0,1",

        "EventCode": "0x2E",

        "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",

        "SampleAfterValue": "200000",
@@ -689,7 +603,6 @@ 
    },

    {

        "BriefDescription": "L2 store requests",

        "Counter": "0,1",

        "EventCode": "0x2A",

        "EventName": "L2_ST.SELF.E_STATE",

        "SampleAfterValue": "200000",
@@ -697,7 +610,6 @@ 
    },

    {

        "BriefDescription": "L2 store requests",

        "Counter": "0,1",

        "EventCode": "0x2A",

        "EventName": "L2_ST.SELF.I_STATE",

        "SampleAfterValue": "200000",
@@ -705,7 +617,6 @@ 
    },

    {

        "BriefDescription": "L2 store requests",

        "Counter": "0,1",

        "EventCode": "0x2A",

        "EventName": "L2_ST.SELF.MESI",

        "SampleAfterValue": "200000",
@@ -713,7 +624,6 @@ 
    },

    {

        "BriefDescription": "L2 store requests",

        "Counter": "0,1",

        "EventCode": "0x2A",

        "EventName": "L2_ST.SELF.M_STATE",

        "SampleAfterValue": "200000",
@@ -721,7 +631,6 @@ 
    },

    {

        "BriefDescription": "L2 store requests",

        "Counter": "0,1",

        "EventCode": "0x2A",

        "EventName": "L2_ST.SELF.S_STATE",

        "SampleAfterValue": "200000",
@@ -729,7 +638,6 @@ 
    },

    {

        "BriefDescription": "Retired loads that hit the L2 cache (precise event).",

        "Counter": "0,1",

        "EventCode": "0xCB",

        "EventName": "MEM_LOAD_RETIRED.L2_HIT",

        "SampleAfterValue": "200000",
@@ -737,7 +645,6 @@ 
    },

    {

        "BriefDescription": "Retired loads that miss the L2 cache",

        "Counter": "0,1",

        "EventCode": "0xCB",

        "EventName": "MEM_LOAD_RETIRED.L2_MISS",

        "SampleAfterValue": "10000",

tools/perf/pmu-events/arch/x86/bonnell/floating-point.json

+5 −42

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tools/perf/pmu-events/arch/x86/bonnell/frontend.json

+0 −11
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "BACLEARS asserted.",

        "Counter": "0,1",

        "EventCode": "0xE6",

        "EventName": "BACLEARS.ANY",

        "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@ 
    },

    {

        "BriefDescription": "Cycles during which instruction fetches are  stalled.",

        "Counter": "0,1",

        "EventCode": "0x86",

        "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",

        "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@ 
    },

    {

        "BriefDescription": "Decode stall due to IQ full",

        "Counter": "0,1",

        "EventCode": "0x87",

        "EventName": "DECODE_STALL.IQ_FULL",

        "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@ 
    },

    {

        "BriefDescription": "Decode stall due to PFB empty",

        "Counter": "0,1",

        "EventCode": "0x87",

        "EventName": "DECODE_STALL.PFB_EMPTY",

        "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@ 
    },

    {

        "BriefDescription": "Instruction fetches.",

        "Counter": "0,1",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@ 
    },

    {

        "BriefDescription": "Icache hit",

        "Counter": "0,1",

        "EventCode": "0x80",

        "EventName": "ICACHE.HIT",

        "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@ 
    },

    {

        "BriefDescription": "Icache miss",

        "Counter": "0,1",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@ 
    },

    {

        "BriefDescription": "All Instructions decoded",

        "Counter": "0,1",

        "EventCode": "0xAA",

        "EventName": "MACRO_INSTS.ALL_DECODED",

        "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@ 
    },

    {

        "BriefDescription": "CISC macro instructions decoded",

        "Counter": "0,1",

        "EventCode": "0xAA",

        "EventName": "MACRO_INSTS.CISC_DECODED",

        "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@ 
    },

    {

        "BriefDescription": "Non-CISC nacro instructions decoded",

        "Counter": "0,1",

        "EventCode": "0xAA",

        "EventName": "MACRO_INSTS.NON_CISC_DECODED",

        "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@ 
    },

    {

        "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",

        "Counter": "0,1",

        "CounterMask": "1",

        "EventCode": "0xA9",

        "EventName": "UOPS.MS_CYCLES",

tools/perf/pmu-events/arch/x86/bonnell/memory.json

+0 −19

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tools/perf/pmu-events/arch/x86/bonnell/other.json

+6 −68

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