Commit 6f90a49b authored by Grigory Vasilyev's avatar Grigory Vasilyev Committed by Alex Deucher
Browse files

drm/amdgpu: Fix incorrect enum type 



Instead of the 'amdgpu_ring_priority_level' type,
the 'amdgpu_gfx_pipe_priority' type was used,
which is an error when setting ring priority.
This is a minor error, but may cause problems in the future.

Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3,
but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with
AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the
code.

Signed-off-by: default avatarGrigory Vasilyev <h0tc0d3@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 02410693

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+1 −1
Original line number Diff line number Diff line
@@ -4741,7 +4741,7 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 
		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)

		+ ring->pipe;

	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?

			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;

			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;

	/* type-2 packets are deprecated on MEC, use type-3 instead */

	r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,

			     hw_prio, NULL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+1 −1
Original line number Diff line number Diff line
@@ -1925,7 +1925,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 
		+ ring->pipe;



	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?

			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;

			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;

	/* type-2 packets are deprecated on MEC, use type-3 instead */

	r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,

			     hw_prio, NULL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+1 −1
Original line number Diff line number Diff line
@@ -2276,7 +2276,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 
		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)

		+ ring->pipe;

	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?

			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;

			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;

	/* type-2 packets are deprecated on MEC, use type-3 instead */

	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,

				hw_prio, NULL);