Commit 6a2b691f authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files

drm/amd/display: wrong VM setting cause invalid DF request from DCN 



fix typo in register field.  we are lucky the shift/mask is the same, no behavior change

add globals to experiment with using different VM settings

Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Reviewed-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0fc899b0

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c

+7 −4
Original line number Diff line number Diff line
@@ -632,6 +632,9 @@ bool min10_is_flip_pending(struct mem_input *mem_input) 
	return false;

}



uint32_t aperture_default_system = 1;

uint32_t context0_default_system; /* = 0;*/



static void min10_set_vm_system_aperture_settings(struct mem_input *mem_input,

		struct vm_system_aperture_param *apt)

{
@@ -645,7 +648,7 @@ static void min10_set_vm_system_aperture_settings(struct mem_input *mem_input, 
	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;



	REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,

		MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */

		MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */

		MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);

	REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,

		MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
@@ -684,9 +687,9 @@ static void min10_set_vm_context0_settings(struct mem_input *mem_input, 
			VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);



	/* fault handling */

	REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,

			VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->fault_default.high_part);

	/* VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, 0 */

	REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,

			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,

			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);

	REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,

			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h

+2 −0
Original line number Diff line number Diff line
@@ -369,6 +369,7 @@ struct dcn_mi_registers { 
	MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\

	MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\

	MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\

	MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\

	MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\

	MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\

	MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
@@ -522,6 +523,7 @@ struct dcn_mi_registers { 
	type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\

	type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\

	type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\

	type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\

	type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\

	type ENABLE_L1_TLB;\

	type SYSTEM_ACCESS_MODE;\