Commit 66cc8838 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_updates_for_v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras 

Pull EDAC updates from Borislav Petkov:

 - A new EDAC driver for Xilinx's Versal integrated memory controller

* tag 'edac_updates_for_v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/versal: Add a Xilinx Versal memory controller driver
  dt-bindings: memory-controllers: Add support for Xilinx Versal EDAC for DDRMC
parents 9e877052 6f15b178

Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)



maintainers:

  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>

  - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>



description:

  The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/

  4X memory interfaces. Versal DDR memory controller has an optional ECC support

  which correct single bit ECC errors and detect double bit ECC errors.



properties:

  compatible:

    const: xlnx,versal-ddrmc



  reg:

    items:

      - description: DDR Memory Controller registers

      - description: NOC registers corresponding to DDR Memory Controller



  reg-names:

    items:

      - const: base

      - const: noc



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - interrupts



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    bus {

      #address-cells = <2>;

      #size-cells = <2>;

      memory-controller@f6150000 {

        compatible = "xlnx,versal-ddrmc";

        reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;

        reg-names = "base", "noc";

        interrupt-parent = <&gic>;

        interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;

      };

    };

MAINTAINERS

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@@ -23738,6 +23738,13 @@ F: Documentation/devicetree/bindings/media/xilinx/ 
F:	drivers/media/platform/xilinx/

F:	include/uapi/linux/xilinx-v4l2-controls.h









XILINX VERSAL EDAC DRIVER









M:	Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>









M:	Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>









S:	Maintained









F:	Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml









F:	drivers/edac/versal_edac.c

















XILINX WATCHDOG DRIVER









M:	Srinivas Neeli <srinivas.neeli@amd.com>









R:	Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>

























drivers/edac/Kconfig



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@@ -561,4 +561,16 @@ config EDAC_NPCM







	  error detection (in-line ECC in which a section 1/8th of the memory









	  device used to store data is used for ECC storage).



















config EDAC_VERSAL









	tristate "Xilinx Versal DDR Memory Controller"









	depends on ARCH_ZYNQMP || COMPILE_TEST









	help









	  Support for error detection and correction on the Xilinx Versal DDR









	  memory controller.



















	  Report both single bit errors (CE) and double bit errors (UE).









	  Support injecting both correctable and uncorrectable errors









	  for debugging purposes.





























endif # EDAC
























drivers/edac/Makefile



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@@ -86,3 +86,4 @@ obj-$(CONFIG_EDAC_BLUEFIELD)		+= bluefield_edac.o







obj-$(CONFIG_EDAC_DMC520)		+= dmc520_edac.o









obj-$(CONFIG_EDAC_NPCM)			+= npcm_edac.o









obj-$(CONFIG_EDAC_ZYNQMP)		+= zynqmp_edac.o









obj-$(CONFIG_EDAC_VERSAL)		+= versal_edac.o
























drivers/edac/versal_edac.c
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