Commit 62b91605 authored by Shawn Guo's avatar Shawn Guo
Browse files

Merge tag 'imx-clk-4.4' into imx/dt 

The i.MX clock updates for 4.4:
 - A couple of fixes on i.MX31 and i.MX35 clock initialization functions
   which makes mxc_timer_init() currently be called twice for DT boot.
 - Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal
   design target.
 - Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for
   Vybrid, and SPDIF_GCLK for i.MX6.
 - A series from Lucas to fix early debug UART clock setup.  This is
   currently a one-off fix for i.MX platform, and can be extended to
   become a generic solution later.
parents 6ff33f39 84a87250

drivers/clk/imx/clk-imx25.c

+12 −0
Original line number Diff line number Diff line
@@ -86,6 +86,16 @@ enum mx25_clks { 


static struct clk *clk[clk_max];



static struct clk ** const uart_clks[] __initconst = {

	&clk[uart_ipg_per],

	&clk[uart1_ipg],

	&clk[uart2_ipg],

	&clk[uart3_ipg],

	&clk[uart4_ipg],

	&clk[uart5_ipg],

	NULL

};



static int __init __mx25_clocks_init(unsigned long osc_rate,

				     void __iomem *ccm_base)

{
@@ -233,6 +243,8 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, 
	 */

	clk_set_parent(clk[cko_sel], clk[ipg]);



	imx_register_uart_clocks(uart_clks);



	return 0;

}

drivers/clk/imx/clk-imx27.c

+13 −0
Original line number Diff line number Diff line
@@ -47,6 +47,17 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; 
static struct clk *clk[IMX27_CLK_MAX];

static struct clk_onecell_data clk_data;



static struct clk ** const uart_clks[] __initconst = {

	&clk[IMX27_CLK_PER1_GATE],

	&clk[IMX27_CLK_UART1_IPG_GATE],

	&clk[IMX27_CLK_UART2_IPG_GATE],

	&clk[IMX27_CLK_UART3_IPG_GATE],

	&clk[IMX27_CLK_UART4_IPG_GATE],

	&clk[IMX27_CLK_UART5_IPG_GATE],

	&clk[IMX27_CLK_UART6_IPG_GATE],

	NULL

};



static void __init _mx27_clocks_init(unsigned long fref)

{

	BUG_ON(!ccm);
@@ -163,6 +174,8 @@ static void __init _mx27_clocks_init(unsigned long fref) 


	clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);



	imx_register_uart_clocks(uart_clks);



	imx_print_silicon_rev("i.MX27", mx27_revision());

}

drivers/clk/imx/clk-imx31.c

+28 −7
Original line number Diff line number Diff line
@@ -62,7 +62,17 @@ enum mx31_clks { 
static struct clk *clk[clk_max];

static struct clk_onecell_data clk_data;



int __init mx31_clocks_init(unsigned long fref)

static struct clk ** const uart_clks[] __initconst = {

	&clk[ipg],

	&clk[uart1_gate],

	&clk[uart2_gate],

	&clk[uart3_gate],

	&clk[uart4_gate],

	&clk[uart5_gate],

	NULL

};



static void __init _mx31_clocks_init(unsigned long fref)

{

	void __iomem *base;

	struct device_node *np;
@@ -132,6 +142,12 @@ int __init mx31_clocks_init(unsigned long fref) 


	imx_check_clocks(clk, ARRAY_SIZE(clk));



	clk_set_parent(clk[csi], clk[upll]);

	clk_prepare_enable(clk[emi_gate]);

	clk_prepare_enable(clk[iim_gate]);

	mx31_revision();

	clk_disable_unprepare(clk[iim_gate]);



	np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");



	if (np) {
@@ -139,6 +155,13 @@ int __init mx31_clocks_init(unsigned long fref) 
		clk_data.clk_num = ARRAY_SIZE(clk);

		of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	}

}



int __init mx31_clocks_init(void)

{

	u32 fref = 26000000; /* default */



	_mx31_clocks_init(fref);



	clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");

	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
@@ -194,12 +217,8 @@ int __init mx31_clocks_init(unsigned long fref) 
	clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");

	clk_register_clkdev(clk[iim_gate], "iim", NULL);



	clk_set_parent(clk[csi], clk[upll]);

	clk_prepare_enable(clk[emi_gate]);

	clk_prepare_enable(clk[iim_gate]);

	mx31_revision();

	clk_disable_unprepare(clk[iim_gate]);



	imx_register_uart_clocks(uart_clks);

	mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);



	return 0;
@@ -218,5 +237,7 @@ int __init mx31_clocks_init_dt(void) 
			break;

	}



	return mx31_clocks_init(fref);

	_mx31_clocks_init(fref);



	return 0;

}

drivers/clk/imx/clk-imx35.c

+37 −22
Original line number Diff line number Diff line
@@ -84,7 +84,15 @@ enum mx35_clks { 


static struct clk *clk[clk_max];



int __init mx35_clocks_init(void)

static struct clk ** const uart_clks[] __initconst = {

	&clk[ipg],

	&clk[uart1_gate],

	&clk[uart2_gate],

	&clk[uart3_gate],

	NULL

};



static void __init _mx35_clocks_init(void)

{

	void __iomem *base;

	u32 pdr0, consumer_sel, hsp_sel;
@@ -220,6 +228,32 @@ int __init mx35_clocks_init(void) 


	imx_check_clocks(clk, ARRAY_SIZE(clk));



	clk_prepare_enable(clk[spba_gate]);

	clk_prepare_enable(clk[gpio1_gate]);

	clk_prepare_enable(clk[gpio2_gate]);

	clk_prepare_enable(clk[gpio3_gate]);

	clk_prepare_enable(clk[iim_gate]);

	clk_prepare_enable(clk[emi_gate]);

	clk_prepare_enable(clk[max_gate]);

	clk_prepare_enable(clk[iomuxc_gate]);



	/*

	 * SCC is needed to boot via mmc after a watchdog reset. The clock code

	 * before conversion to common clk also enabled UART1 (which isn't

	 * handled here and not needed for mmc) and IIM (which is enabled

	 * unconditionally above).

	 */

	clk_prepare_enable(clk[scc_gate]);



	imx_register_uart_clocks(uart_clks);



	imx_print_silicon_rev("i.MX35", mx35_revision());

}



int __init mx35_clocks_init(void)

{

	_mx35_clocks_init();



	clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");

	clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");

	clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
@@ -279,25 +313,6 @@ int __init mx35_clocks_init(void) 
	clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");

	clk_register_clkdev(clk[admux_gate], "audmux", NULL);



	clk_prepare_enable(clk[spba_gate]);

	clk_prepare_enable(clk[gpio1_gate]);

	clk_prepare_enable(clk[gpio2_gate]);

	clk_prepare_enable(clk[gpio3_gate]);

	clk_prepare_enable(clk[iim_gate]);

	clk_prepare_enable(clk[emi_gate]);

	clk_prepare_enable(clk[max_gate]);

	clk_prepare_enable(clk[iomuxc_gate]);



	/*

	 * SCC is needed to boot via mmc after a watchdog reset. The clock code

	 * before conversion to common clk also enabled UART1 (which isn't

	 * handled here and not needed for mmc) and IIM (which is enabled

	 * unconditionally above).

	 */

	clk_prepare_enable(clk[scc_gate]);



	imx_print_silicon_rev("i.MX35", mx35_revision());



	mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);



	return 0;
@@ -305,10 +320,10 @@ int __init mx35_clocks_init(void) 


static void __init mx35_clocks_init_dt(struct device_node *ccm_node)

{

	_mx35_clocks_init();



	clk_data.clks = clk;

	clk_data.clk_num = ARRAY_SIZE(clk);

	of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);



	mx35_clocks_init();

}

CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);

drivers/clk/imx/clk-imx51-imx53.c

+16 −0
Original line number Diff line number Diff line
@@ -130,6 +130,20 @@ static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" }; 
static struct clk *clk[IMX5_CLK_END];

static struct clk_onecell_data clk_data;



static struct clk ** const uart_clks[] __initconst = {

	&clk[IMX5_CLK_UART1_IPG_GATE],

	&clk[IMX5_CLK_UART1_PER_GATE],

	&clk[IMX5_CLK_UART2_IPG_GATE],

	&clk[IMX5_CLK_UART2_PER_GATE],

	&clk[IMX5_CLK_UART3_IPG_GATE],

	&clk[IMX5_CLK_UART3_PER_GATE],

	&clk[IMX5_CLK_UART4_IPG_GATE],

	&clk[IMX5_CLK_UART4_PER_GATE],

	&clk[IMX5_CLK_UART5_IPG_GATE],

	&clk[IMX5_CLK_UART5_PER_GATE],

	NULL

};



static void __init mx5_clocks_common_init(void __iomem *ccm_base)

{

	clk[IMX5_CLK_DUMMY]		= imx_clk_fixed("dummy", 0);
@@ -310,6 +324,8 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) 
	clk_prepare_enable(clk[IMX5_CLK_TMAX1]);

	clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */

	clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */



	imx_register_uart_clocks(uart_clks);

}



static void __init mx50_clocks_init(struct device_node *np)