staging: ti dspbridge: add header files (6280238c) · Commits · github.com / kvm-riscv / linux

drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h

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		/*
		* _chnl_sm.h
		*
		* DSP-BIOS Bridge driver support functions for TI OMAP processors.
		*
		* Private header file defining channel manager and channel objects for
		* a shared memory channel driver.
		*
		* Shared between the modules implementing the shared memory channel class
		* library.
		*
		* Copyright (C) 2005-2006 Texas Instruments, Inc.
		*
		* This package is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
		* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
		* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
		*/

		#ifndef _CHNL_SM_
		#define _CHNL_SM_

		#include <dspbridge/dspapi.h>
		#include <dspbridge/dspdefs.h>

		#include <dspbridge/list.h>
		#include <dspbridge/ntfy.h>

		/*
		* These target side symbols define the beginning and ending addresses
		* of shared memory buffer. They are defined in the *cfg.cmd file by
		* cdb code.
		*/
		#define CHNL_SHARED_BUFFER_BASE_SYM "_SHM_BEG"
		#define CHNL_SHARED_BUFFER_LIMIT_SYM "_SHM_END"
		#define BRIDGEINIT_BIOSGPTIMER "_BRIDGEINIT_BIOSGPTIMER"
		#define BRIDGEINIT_LOADMON_GPTIMER "_BRIDGEINIT_LOADMON_GPTIMER"

		#ifndef _CHNL_WORDSIZE
		#define _CHNL_WORDSIZE 4 /* default _CHNL_WORDSIZE is 2 bytes/word */
		#endif

		#define MAXOPPS 16

		/* Shared memory config options */
		#define SHM_CURROPP 0 /* Set current OPP in shm */
		#define SHM_OPPINFO 1 /* Set dsp voltage and freq table values */
		#define SHM_GETOPP 2 /* Get opp requested by DSP */

		struct opp_table_entry {
		u32 voltage;
		u32 frequency;
		u32 min_freq;
		u32 max_freq;
		};

		struct opp_struct {
		u32 curr_opp_pt;
		u32 num_opp_pts;
		struct opp_table_entry opp_point[MAXOPPS];
		};

		/* Request to MPU */
		struct opp_rqst_struct {
		u32 rqst_dsp_freq;
		u32 rqst_opp_pt;
		};

		/* Info to MPU */
		struct load_mon_struct {
		u32 curr_dsp_load;
		u32 curr_dsp_freq;
		u32 pred_dsp_load;
		u32 pred_dsp_freq;
		};

		/* Structure in shared between DSP and PC for communication. */
		struct shm {
		u32 dsp_free_mask; /* Written by DSP, read by PC. */
		u32 host_free_mask; /* Written by PC, read by DSP */

		u32 input_full; /* Input channel has unread data. */
		u32 input_id; /* Channel for which input is available. */
		u32 input_size; /* Size of data block (in DSP words). */

		u32 output_full; /* Output channel has unread data. */
		u32 output_id; /* Channel for which output is available. */
		u32 output_size; /* Size of data block (in DSP words). */

		u32 arg; /* Arg for Issue/Reclaim (23 bits for 55x). */
		u32 resvd; /* Keep structure size even for 32-bit DSPs */

		/* Operating Point structure */
		struct opp_struct opp_table_struct;
		/* Operating Point Request structure */
		struct opp_rqst_struct opp_request;
		/* load monitor information structure */
		struct load_mon_struct load_mon_info;
		#ifdef CONFIG_BRIDGE_WDT3
		/* Flag for WDT enable/disable F/I clocks */
		u32 wdt_setclocks;
		u32 wdt_overflow; /* WDT overflow time */
		char dummy[176]; /* padding to 256 byte boundary */
		#else
		char dummy[184]; /* padding to 256 byte boundary */
		#endif
		u32 shm_dbg_var[64]; /* shared memory debug variables */
		};

		/* Channel Manager: only one created per board: */
		struct chnl_mgr {
		/* Function interface to Bridge driver */
		struct bridge_drv_interface *intf_fxns;
		struct io_mgr hio_mgr; / IO manager */
		/* Device this board represents */
		struct dev_object *hdev_obj;

		/* These fields initialized in bridge_chnl_create(): */
		u32 dw_output_mask; /* Host output channels w/ full buffers */
		u32 dw_last_output; /* Last output channel fired from DPC */
		/* Critical section object handle */
		spinlock_t chnl_mgr_lock;
		u32 word_size; /* Size in bytes of DSP word */
		u8 max_channels; /* Total number of channels */
		u8 open_channels; /* Total number of open channels */
		struct chnl_object *ap_channel; / Array of channels */
		u8 dw_type; /* Type of channel class library */
		/* If no shm syms, return for CHNL_Open */
		int chnl_open_status;
		};

		/*
		* Channel: up to CHNL_MAXCHANNELS per board or if DSP-DMA supported then
		* up to CHNL_MAXCHANNELS + CHNL_MAXDDMACHNLS per board.
		*/
		struct chnl_object {
		/* Pointer back to channel manager */
		struct chnl_mgr *chnl_mgr_obj;
		u32 chnl_id; /* Channel id */
		u8 dw_state; /* Current channel state */
		s8 chnl_mode; /* Chnl mode and attributes */
		/* Chnl I/O completion event (user mode) */
		void *user_event;
		/* Abstract syncronization object */
		struct sync_object *sync_event;
		u32 process; /* Process which created this channel */
		u32 pcb_arg; /* Argument to use with callback */
		struct lst_list pio_requests; / List of IOR's to driver */
		s32 cio_cs; /* Number of IOC's in queue */
		s32 cio_reqs; /* Number of IORequests in queue */
		s32 chnl_packets; /* Initial number of free Irps */
		/* List of IOC's from driver */
		struct lst_list *pio_completions;
		struct lst_list free_packets_list; / List of free Irps */
		struct ntfy_object *ntfy_obj;
		u32 bytes_moved; /* Total number of bytes transfered */

		/* For DSP-DMA */

		/* Type of chnl transport:CHNL_[PCPY][DDMA] */
		u32 chnl_type;
		};

		/* I/O Request/completion packet: */
		struct chnl_irp {
		struct list_head link; /* Link to next CHIRP in queue. */
		/* Buffer to be filled/emptied. (User) */
		u8 *host_user_buf;
		/* Buffer to be filled/emptied. (System) */
		u8 *host_sys_buf;
		u32 dw_arg; /* Issue/Reclaim argument. */
		u32 dsp_tx_addr; /* Transfer address on DSP side. */
		u32 byte_size; /* Bytes transferred. */
		u32 buf_size; /* Actual buffer size when allocated. */
		u32 status; /* Status of IO completion. */
		};

		#endif /* _CHNL_SM_ */

drivers/staging/tidspbridge/include/dspbridge/brddefs.h

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		/*
		* brddefs.h
		*
		* DSP-BIOS Bridge driver support functions for TI OMAP processors.
		*
		* Global BRD constants and types, shared between DSP API and Bridge driver.
		*
		* Copyright (C) 2005-2006 Texas Instruments, Inc.
		*
		* This package is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
		* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
		* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
		*/

		#ifndef BRDDEFS_
		#define BRDDEFS_

		/* platform status values */
		#define BRD_STOPPED 0x0 /* No Monitor Loaded, Not running. */
		#define BRD_IDLE 0x1 /* Monitor Loaded, but suspended. */
		#define BRD_RUNNING 0x2 /* Monitor loaded, and executing. */
		#define BRD_UNKNOWN 0x3 /* Board state is indeterminate. */
		#define BRD_SYNCINIT 0x4
		#define BRD_LOADED 0x5
		#define BRD_LASTSTATE BRD_LOADED /* Set to highest legal board state. */
		#define BRD_SLEEP_TRANSITION 0x6 /* Sleep transition in progress */
		#define BRD_HIBERNATION 0x7 /* MPU initiated hibernation */
		#define BRD_RETENTION 0x8 /* Retention mode */
		#define BRD_DSP_HIBERNATION 0x9 /* DSP initiated hibernation */
		#define BRD_ERROR 0xA /* Board state is Error */

		/* BRD Object */
		struct brd_object;

		#endif /* BRDDEFS_ */

drivers/staging/tidspbridge/include/dspbridge/cfg.h

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		/*
		* cfg.h
		*
		* DSP-BIOS Bridge driver support functions for TI OMAP processors.
		*
		* PM Configuration module.
		*
		* Copyright (C) 2005-2006 Texas Instruments, Inc.
		*
		* This package is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
		* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
		* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
		*/

		#ifndef CFG_
		#define CFG_
		#include <dspbridge/host_os.h>
		#include <dspbridge/cfgdefs.h>

		/*
		* ======== cfg_exit ========
		* Purpose:
		* Discontinue usage of the CFG module.
		* Parameters:
		* Returns:
		* Requires:
		* cfg_init(void) was previously called.
		* Ensures:
		* Resources acquired in cfg_init(void) are freed.
		*/
		extern void cfg_exit(void);

		/*
		* ======== cfg_get_auto_start ========
		* Purpose:
		* Retreive the autostart mask, if any, for this board.
		* Parameters:
		* dev_node_obj: Handle to the dev_node who's driver we are querying.
		* pdwAutoStart: Ptr to location for 32 bit autostart mask.
		* Returns:
		* 0: Success.
		* -EFAULT: dev_node_obj is invalid.
		* -ENODATA: Unable to retreive resource.
		* Requires:
		* CFG initialized.
		* Ensures:
		* 0: *pdwAutoStart contains autostart mask for this devnode.
		*/
		extern int cfg_get_auto_start(IN struct cfg_devnode *dev_node_obj,
		OUT u32 *pdwAutoStart);

		/*
		* ======== cfg_get_cd_version ========
		* Purpose:
		* Retrieves the version of the PM Class Driver.
		* Parameters:
		* pdwVersion: Ptr to u32 to contain version number upon return.
		* Returns:
		* 0: Success. pdwVersion contains Class Driver version in
		* the form: 0xAABBCCDD where AABB is Major version and
		* CCDD is Minor.
		* -EPERM: Failure.
		* Requires:
		* CFG initialized.
		* Ensures:
		* 0: Success.
		* else: *pdwVersion is NULL.
		*/
		extern int cfg_get_cd_version(OUT u32 *pdwVersion);

		/*
		* ======== cfg_get_dev_object ========
		* Purpose:
		* Retrieve the Device Object handle for a given devnode.
		* Parameters:
		* dev_node_obj: Platform's dev_node handle from which to retrieve
		* value.
		* pdwValue: Ptr to location to store the value.
		* Returns:
		* 0: Success.
		* -EFAULT: dev_node_obj is invalid or phDevObject is invalid.
		* -ENODATA: The resource is not available.
		* Requires:
		* CFG initialized.
		* Ensures:
		* 0: *pdwValue is set to the retrieved u32.
		* else: *pdwValue is set to 0L.
		*/
		extern int cfg_get_dev_object(IN struct cfg_devnode *dev_node_obj,
		OUT u32 *pdwValue);

		/*
		* ======== cfg_get_exec_file ========
		* Purpose:
		* Retreive the default executable, if any, for this board.
		* Parameters:
		* dev_node_obj: Handle to the dev_node who's driver we are querying.
		* buf_size: Size of buffer.
		* pstrExecFile: Ptr to character buf to hold ExecFile.
		* Returns:
		* 0: Success.
		* -EFAULT: dev_node_obj is invalid or pstrExecFile is invalid.
		* -ENODATA: The resource is not available.
		* Requires:
		* CFG initialized.
		* Ensures:
		* 0: Not more than buf_size bytes were copied into pstrExecFile,
		* and *pstrExecFile contains default executable for this
		* devnode.
		*/
		extern int cfg_get_exec_file(IN struct cfg_devnode *dev_node_obj,
		IN u32 buf_size, OUT char *pstrExecFile);

		/*
		* ======== cfg_get_object ========
		* Purpose:
		* Retrieve the Driver Object handle From the Registry
		* Parameters:
		* pdwValue: Ptr to location to store the value.
		* dw_type Type of Object to Get
		* Returns:
		* 0: Success.
		* Requires:
		* CFG initialized.
		* Ensures:
		* 0: *pdwValue is set to the retrieved u32(non-Zero).
		* else: *pdwValue is set to 0L.
		*/
		extern int cfg_get_object(OUT u32 *pdwValue, u8 dw_type);

		/*
		* ======== cfg_get_perf_value ========
		* Purpose:
		* Retrieve a flag indicating whether PERF should log statistics for the
		* PM class driver.
		* Parameters:
		* pfEnablePerf: Location to store flag. 0 indicates the key was
		* not found, or had a zero value. A nonzero value
		* means the key was found and had a nonzero value.
		* Returns:
		* Requires:
		* pfEnablePerf != NULL;
		* Ensures:
		*/
		extern void cfg_get_perf_value(OUT bool *pfEnablePerf);

		/*
		* ======== cfg_get_zl_file ========
		* Purpose:
		* Retreive the ZLFile, if any, for this board.
		* Parameters:
		* dev_node_obj: Handle to the dev_node who's driver we are querying.
		* buf_size: Size of buffer.
		* pstrZLFileName: Ptr to character buf to hold ZLFileName.
		* Returns:
		* 0: Success.
		* -EFAULT: pstrZLFileName is invalid or dev_node_obj is invalid.
		* -ENODATA: couldn't find the ZLFileName.
		* Requires:
		* CFG initialized.
		* Ensures:
		* 0: Not more than buf_size bytes were copied into
		* pstrZLFileName, and *pstrZLFileName contains ZLFileName
		* for this devnode.
		*/
		extern int cfg_get_zl_file(IN struct cfg_devnode *dev_node_obj,
		IN u32 buf_size, OUT char *pstrZLFileName);

		/*
		* ======== cfg_init ========
		* Purpose:
		* Initialize the CFG module's private state.
		* Parameters:
		* Returns:
		* TRUE if initialized; FALSE if error occured.
		* Requires:
		* Ensures:
		* A requirement for each of the other public CFG functions.
		*/
		extern bool cfg_init(void);

		/*
		* ======== cfg_set_dev_object ========
		* Purpose:
		* Store the Device Object handle for a given devnode.
		* Parameters:
		* dev_node_obj: Platform's dev_node handle we are storing value with.
		* dwValue: Arbitrary value to store.
		* Returns:
		* 0: Success.
		* -EFAULT: dev_node_obj is invalid.
		* -EPERM: Internal Error.
		* Requires:
		* CFG initialized.
		* Ensures:
		* 0: The Private u32 was successfully set.
		*/
		extern int cfg_set_dev_object(IN struct cfg_devnode *dev_node_obj,
		IN u32 dwValue);

		/*
		* ======== CFG_SetDrvObject ========
		* Purpose:
		* Store the Driver Object handle.
		* Parameters:
		* dwValue: Arbitrary value to store.
		* dw_type Type of Object to Store
		* Returns:
		* 0: Success.
		* -EPERM: Internal Error.
		* Requires:
		* CFG initialized.
		* Ensures:
		* 0: The Private u32 was successfully set.
		*/
		extern int cfg_set_object(IN u32 dwValue, u8 dw_type);

		#endif /* CFG_ */

drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h

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		/*
		* cfgdefs.h
		*
		* DSP-BIOS Bridge driver support functions for TI OMAP processors.
		*
		* Global CFG constants and types, shared between DSP API and Bridge driver.
		*
		* Copyright (C) 2005-2006 Texas Instruments, Inc.
		*
		* This package is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
		* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
		* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
		*/

		#ifndef CFGDEFS_
		#define CFGDEFS_

		/* Maximum length of module search path. */
		#define CFG_MAXSEARCHPATHLEN 255

		/* Maximum length of general paths. */
		#define CFG_MAXPATH 255

		/* Host Resources: */
		#define CFG_MAXMEMREGISTERS 9
		#define CFG_MAXIOPORTS 20
		#define CFG_MAXIRQS 7
		#define CFG_MAXDMACHANNELS 7

		/* IRQ flag */
		#define CFG_IRQSHARED 0x01 /* IRQ can be shared */

		/* DSP Resources: */
		#define CFG_DSPMAXMEMTYPES 10
		#define CFG_DEFAULT_NUM_WINDOWS 1 /* We support only one window. */

		/* A platform-related device handle: */
		struct cfg_devnode;

		/*
		* Host resource structure.
		*/
		struct cfg_hostres {
		u32 num_mem_windows; /* Set to default */
		/* This is the base.memory */
		u32 dw_mem_base[CFG_MAXMEMREGISTERS]; /* shm virtual address */
		u32 dw_mem_length[CFG_MAXMEMREGISTERS]; /* Length of the Base */
		u32 dw_mem_phys[CFG_MAXMEMREGISTERS]; /* shm Physical address */
		u8 birq_registers; /* IRQ Number */
		u8 birq_attrib; /* IRQ Attribute */
		u32 dw_offset_for_monitor; /* The Shared memory starts from
		* dw_mem_base + this offset */
		/*
		* Info needed by NODE for allocating channels to communicate with RMS:
		* dw_chnl_offset: Offset of RMS channels. Lower channels are
		* reserved.
		* dw_chnl_buf_size: Size of channel buffer to send to RMS
		* dw_num_chnls: Total number of channels
		* (including reserved).
		*/
		u32 dw_chnl_offset;
		u32 dw_chnl_buf_size;
		u32 dw_num_chnls;
		void __iomem *dw_per_base;
		u32 dw_per_pm_base;
		u32 dw_core_pm_base;
		void __iomem *dw_dmmu_base;
		void __iomem *dw_sys_ctrl_base;
		};

		struct cfg_dspmemdesc {
		u32 mem_type; /* Type of memory. */
		u32 ul_min; /* Minimum amount of memory of this type. */
		u32 ul_max; /* Maximum amount of memory of this type. */
		};

		#endif /* CFGDEFS_ */

drivers/staging/tidspbridge/include/dspbridge/chnl.h

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		/*
		* chnl.h
		*
		* DSP-BIOS Bridge driver support functions for TI OMAP processors.
		*
		* DSP API channel interface: multiplexes data streams through the single
		* physical link managed by a Bridge driver.
		*
		* See DSP API chnl.h for more details.
		*
		* Copyright (C) 2005-2006 Texas Instruments, Inc.
		*
		* This package is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
		* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
		* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
		*/

		#ifndef CHNL_
		#define CHNL_

		#include <dspbridge/chnlpriv.h>

		/*
		* ======== chnl_close ========
		* Purpose:
		* Ensures all pending I/O on this channel is cancelled, discards all
		* queued I/O completion notifications, then frees the resources allocated
		* for this channel, and makes the corresponding logical channel id
		* available for subsequent use.
		* Parameters:
		* chnl_obj: Channel object handle.
		* Returns:
		* 0: Success;
		* -EFAULT: Invalid chnl_obj.
		* Requires:
		* chnl_init(void) called.
		* No thread must be blocked on this channel's I/O completion event.
		* Ensures:
		* 0: The I/O completion event for this channel is freed.
		* chnl_obj is no longer valid.
		*/
		extern int chnl_close(struct chnl_object *chnl_obj);

		/*
		* ======== chnl_create ========
		* Purpose:
		* Create a channel manager object, responsible for opening new channels
		* and closing old ones for a given board.
		* Parameters:
		* phChnlMgr: Location to store a channel manager object on output.
		* hdev_obj: Handle to a device object.
		* pMgrAttrs: Channel manager attributes.
		* pMgrAttrs->max_channels: Max channels
		* pMgrAttrs->birq: Channel's I/O IRQ number.
		* pMgrAttrs->irq_shared: TRUE if the IRQ is shareable.
		* pMgrAttrs->word_size: DSP Word size in equivalent PC bytes..
		* Returns:
		* 0: Success;
		* -EFAULT: hdev_obj is invalid.
		* -EINVAL: max_channels is 0.
		* Invalid DSP word size (must be > 0).
		* Invalid base address for DSP communications.
		* -ENOMEM: Insufficient memory for requested resources.
		* -EIO: Unable to plug channel ISR for configured IRQ.
		* -ECHRNG: This manager cannot handle this many channels.
		* -EEXIST: Channel manager already exists for this device.
		* Requires:
		* chnl_init(void) called.
		* phChnlMgr != NULL.
		* pMgrAttrs != NULL.
		* Ensures:
		* 0: Subsequent calls to chnl_create() for the same
		* board without an intervening call to
		* chnl_destroy() will fail.
		*/
		extern int chnl_create(OUT struct chnl_mgr **phChnlMgr,
		struct dev_object *hdev_obj,
		IN CONST struct chnl_mgrattrs *pMgrAttrs);

		/*
		* ======== chnl_destroy ========
		* Purpose:
		* Close all open channels, and destroy the channel manager.
		* Parameters:
		* hchnl_mgr: Channel manager object.
		* Returns:
		* 0: Success.
		* -EFAULT: hchnl_mgr was invalid.
		* Requires:
		* chnl_init(void) called.
		* Ensures:
		* 0: Cancels I/O on each open channel.
		* Closes each open channel.
		* chnl_create may subsequently be called for the
		* same board.
		*/
		extern int chnl_destroy(struct chnl_mgr *hchnl_mgr);

		/*
		* ======== chnl_exit ========
		* Purpose:
		* Discontinue usage of the CHNL module.
		* Parameters:
		* Returns:
		* Requires:
		* chnl_init(void) previously called.
		* Ensures:
		* Resources, if any acquired in chnl_init(void), are freed when the last
		* client of CHNL calls chnl_exit(void).
		*/
		extern void chnl_exit(void);

		/*
		* ======== chnl_init ========
		* Purpose:
		* Initialize the CHNL module's private state.
		* Parameters:
		* Returns:
		* TRUE if initialized; FALSE if error occurred.
		* Requires:
		* Ensures:
		* A requirement for each of the other public CHNL functions.
		*/
		extern bool chnl_init(void);

		#endif /* CHNL_ */