Commit 5b7e3499 authored by Johan Hovold's avatar Johan Hovold Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: reorder USB interrupts 



Three SoCs did not follow the interrupt order specified by the USB
controller binding.

While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.

Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
[bjorn: Omitted sdx65 part from this patch]
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org
parent 2a8d28b8

arch/arm64/boot/dts/qcom/sm8250.dtsi

+12 −8
Original line number Diff line number Diff line
@@ -3018,11 +3018,13 @@ usb_1: usb@a6f8800 { 
			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",

					  "dm_hs_phy_irq", "ss_phy_irq";

					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>;

			interrupt-names = "hs_phy_irq",

					  "ss_phy_irq",

					  "dm_hs_phy_irq",

					  "dp_hs_phy_irq";



			power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -3073,11 +3075,13 @@ usb_2: usb@a8f8800 { 
			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",

					  "dm_hs_phy_irq", "ss_phy_irq";

					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>;

			interrupt-names = "hs_phy_irq",

					  "ss_phy_irq",

					  "dm_hs_phy_irq",

					  "dp_hs_phy_irq";



			power-domains = <&gcc USB30_SEC_GDSC>;

arch/arm64/boot/dts/qcom/sm8350.dtsi

+12 −8
Original line number Diff line number Diff line
@@ -2461,11 +2461,13 @@ usb_1: usb@a6f8800 { 
			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",

					  "dm_hs_phy_irq", "ss_phy_irq";

					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>;

			interrupt-names = "hs_phy_irq",

					  "ss_phy_irq",

					  "dm_hs_phy_irq",

					  "dp_hs_phy_irq";



			power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -2509,11 +2511,13 @@ usb_2: usb@a8f8800 { 
			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",

					  "dm_hs_phy_irq", "ss_phy_irq";

					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>;

			interrupt-names = "hs_phy_irq",

					  "ss_phy_irq",

					  "dm_hs_phy_irq",

					  "dp_hs_phy_irq";



			power-domains = <&gcc USB30_SEC_GDSC>;