Commit 5b565e0e authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: expose the VA above the hole to userspace



Let userspace know how much area we have above the 48bit VA hole on
Vega10.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4b7f0848
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+10 −2
Original line number Diff line number Diff line
@@ -550,6 +550,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
	}
	case AMDGPU_INFO_DEV_INFO: {
		struct drm_amdgpu_info_device dev_info = {};
		uint64_t vm_size;

		dev_info.device_id = dev->pdev->device;
		dev_info.chip_rev = adev->rev_id;
@@ -577,10 +578,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
			dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
		if (amdgpu_sriov_vf(adev))
			dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;

		vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
		dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
		dev_info.virtual_address_max =
			min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE,
			    AMDGPU_VA_HOLE_START);
			min(vm_size, AMDGPU_VA_HOLE_START);

		vm_size -= AMDGPU_VA_RESERVED_SIZE;
		if (vm_size > AMDGPU_VA_HOLE_START) {
			dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
			dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
		}
		dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
		dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
		dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
+4 −0
Original line number Diff line number Diff line
@@ -877,6 +877,10 @@ struct drm_amdgpu_info_device {
	__u32 _pad1;
	/* always on cu bitmap */
	__u32 cu_ao_bitmap[4][4];
	/** Starting high virtual address for UMDs. */
	__u64 high_va_offset;
	/** The maximum high virtual address */
	__u64 high_va_max;
};

struct drm_amdgpu_info_hw_ip {