Commit 68f8eb19 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes 



Add SCIF[1-4] nodes to r9a07g044 (RZ/G2L) SoC DTSI.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103195600.23964-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1ab0a62f

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+72 −0
Original line number Diff line number Diff line
@@ -194,6 +194,78 @@ scif0: serial@1004b800 { 
			status = "disabled";

		};



		scif1: serial@1004bc00 {

			compatible = "renesas,scif-r9a07g044";

			reg = <0 0x1004bc00 0 0x400>;

			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "eri", "rxi", "txi",

					  "bri", "dri", "tei";

			clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;

			clock-names = "fck";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;

			status = "disabled";

		};



		scif2: serial@1004c000 {

			compatible = "renesas,scif-r9a07g044";

			reg = <0 0x1004c000 0 0x400>;

			interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "eri", "rxi", "txi",

					  "bri", "dri", "tei";

			clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;

			clock-names = "fck";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;

			status = "disabled";

		};



		scif3: serial@1004c400 {

			compatible = "renesas,scif-r9a07g044";

			reg = <0 0x1004c400 0 0x400>;

			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "eri", "rxi", "txi",

					  "bri", "dri", "tei";

			clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;

			clock-names = "fck";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;

			status = "disabled";

		};



		scif4: serial@1004c800 {

			compatible = "renesas,scif-r9a07g044";

			reg = <0 0x1004c800 0 0x400>;

			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "eri", "rxi", "txi",

					  "bri", "dri", "tei";

			clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;

			clock-names = "fck";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;

			status = "disabled";

		};



		canfd: can@10050000 {

			compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";

			reg = <0 0x10050000 0 0x8000>;