Commit 59a7d68b authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g044: Add OSTM nodes 



Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211118191826.2026-2-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5fcf8b06

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -791,6 +791,39 @@ hsusb: usb@11c60000 { 
			power-domains = <&cpg>;

			status = "disabled";

		};



		ostm0: timer@12801000 {

			compatible = "renesas,r9a07g044-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801000 0x0 0x400>;

			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;

			resets = <&cpg R9A07G044_OSTM0_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		ostm1: timer@12801400 {

			compatible = "renesas,r9a07g044-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801400 0x0 0x400>;

			interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;

			resets = <&cpg R9A07G044_OSTM1_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		ostm2: timer@12801800 {

			compatible = "renesas,r9a07g044-ostm",

				     "renesas,ostm";

			reg = <0x0 0x12801800 0x0 0x400>;

			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;

			resets = <&cpg R9A07G044_OSTM2_PRESETZ>;

			power-domains = <&cpg>;

			status = "disabled";

		};

	};



	timer {