Commit 5621739d authored by Ulrich Hecht's avatar Ulrich Hecht Committed by Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions 



This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the
R8A779A0 (V3U) SoC.

Signed-off-by: default avatarUlrich Hecht <uli+renesas@fpond.eu>
Tested-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-6-uli+renesas@fpond.eu


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 741a7370

drivers/pinctrl/renesas/pfc-r8a779a0.c

+156 −0
Original line number Diff line number Diff line
@@ -1233,10 +1233,166 @@ static const struct sh_pfc_pin pinmux_pins[] = { 
	PINMUX_GPIO_GP_ALL(),

};



/* - SCIF0 ------------------------------------------------------------------ */

static const unsigned int scif0_data_pins[] = {

	/* RX0, TX0 */

	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),

};

static const unsigned int scif0_data_mux[] = {

	RX0_MARK, TX0_MARK,

};

static const unsigned int scif0_clk_pins[] = {

	/* SCK0 */

	RCAR_GP_PIN(1, 2),

};

static const unsigned int scif0_clk_mux[] = {

	SCK0_MARK,

};

static const unsigned int scif0_ctrl_pins[] = {

	/* RTS0#, CTS0# */

	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),

};

static const unsigned int scif0_ctrl_mux[] = {

	RTS0_N_MARK, CTS0_N_MARK,

};



/* - SCIF1 ------------------------------------------------------------------ */

static const unsigned int scif1_data_a_pins[] = {

	/* RX, TX */

	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),

};

static const unsigned int scif1_data_a_mux[] = {

	RX1_A_MARK, TX1_A_MARK,

};

static const unsigned int scif1_data_b_pins[] = {

	/* RX, TX */

	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1),

};

static const unsigned int scif1_data_b_mux[] = {

	RX1_B_MARK, TX1_B_MARK,

};

static const unsigned int scif1_clk_pins[] = {

	/* SCK1 */

	RCAR_GP_PIN(1, 18),

};

static const unsigned int scif1_clk_mux[] = {

	SCK1_MARK,

};

static const unsigned int scif1_ctrl_pins[] = {

	/* RTS1#, CTS1# */

	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),

};

static const unsigned int scif1_ctrl_mux[] = {

	RTS1_N_MARK, CTS1_N_MARK,

};



/* - SCIF3 ------------------------------------------------------------------ */

static const unsigned int scif3_data_pins[] = {

	/* RX3, TX3 */

	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),

};

static const unsigned int scif3_data_mux[] = {

	RX3_MARK, TX3_MARK,

};

static const unsigned int scif3_clk_pins[] = {

	/* SCK3 */

	RCAR_GP_PIN(1, 13),

};

static const unsigned int scif3_clk_mux[] = {

	SCK3_MARK,

};

static const unsigned int scif3_ctrl_pins[] = {

	/* RTS3#, CTS3# */

	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),

};

static const unsigned int scif3_ctrl_mux[] = {

	RTS3_N_MARK, CTS3_N_MARK,

};



/* - SCIF4 ------------------------------------------------------------------ */

static const unsigned int scif4_data_pins[] = {

	/* RX4, TX4 */

	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),

};

static const unsigned int scif4_data_mux[] = {

	RX4_MARK, TX4_MARK,

};

static const unsigned int scif4_clk_pins[] = {

	/* SCK4 */

	RCAR_GP_PIN(2, 5),

};

static const unsigned int scif4_clk_mux[] = {

	SCK4_MARK,

};

static const unsigned int scif4_ctrl_pins[] = {

	/* RTS4#, CTS4# */

	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),

};

static const unsigned int scif4_ctrl_mux[] = {

	RTS4_N_MARK, CTS4_N_MARK,

};



/* - SCIF Clock ------------------------------------------------------------- */

static const unsigned int scif_clk_pins[] = {

	/* SCIF_CLK */

	RCAR_GP_PIN(1, 0),

};

static const unsigned int scif_clk_mux[] = {

	SCIF_CLK_MARK,

};



static const struct sh_pfc_pin_group pinmux_groups[] = {

	SH_PFC_PIN_GROUP(scif0_data),

	SH_PFC_PIN_GROUP(scif0_clk),

	SH_PFC_PIN_GROUP(scif0_ctrl),

	SH_PFC_PIN_GROUP(scif1_data_a),

	SH_PFC_PIN_GROUP(scif1_data_b),

	SH_PFC_PIN_GROUP(scif1_clk),

	SH_PFC_PIN_GROUP(scif1_ctrl),

	SH_PFC_PIN_GROUP(scif3_data),

	SH_PFC_PIN_GROUP(scif3_clk),

	SH_PFC_PIN_GROUP(scif3_ctrl),

	SH_PFC_PIN_GROUP(scif4_data),

	SH_PFC_PIN_GROUP(scif4_clk),

	SH_PFC_PIN_GROUP(scif4_ctrl),

	SH_PFC_PIN_GROUP(scif_clk),

};



static const char * const scif0_groups[] = {

	"scif0_data",

	"scif0_clk",

	"scif0_ctrl",

};



static const char * const scif1_groups[] = {

	"scif1_data_a",

	"scif1_data_b",

	"scif1_clk",

	"scif1_ctrl",

};



static const char * const scif3_groups[] = {

	"scif3_data",

	"scif3_clk",

	"scif3_ctrl",

};



static const char * const scif4_groups[] = {

	"scif4_data",

	"scif4_clk",

	"scif4_ctrl",

};



static const char * const scif_clk_groups[] = {

	"scif_clk",

};



static const struct sh_pfc_function pinmux_functions[] = {

	SH_PFC_FUNCTION(scif0),

	SH_PFC_FUNCTION(scif1),

	SH_PFC_FUNCTION(scif3),

	SH_PFC_FUNCTION(scif4),

	SH_PFC_FUNCTION(scif_clk),

};



static const struct pinmux_cfg_reg pinmux_config_regs[] = {