Commit 55b72855 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2023-10-19' of... 

Merge tag 'drm-intel-gt-next-2023-10-19' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

Driver Changes:

Fixes/improvements/new stuff:

- Retry gtt fault when out of fence registers (Ville Syrjälä)
- Determine context valid in OA reports [perf] (Umesh Nerlige Ramappa)

Future platform enablement:

- GuC based TLB invalidation for Meteorlake (Jonathan Cavitt, Prathap Kumar Valsan)
- Don't set PIPE_CONTROL_FLUSH_L3 [mtl] (Vinay Belgaumkar)

Miscellaneous:

- Clean up zero initializers [guc,pxp] (Ville Syrjälä)
- Prevent potential null-ptr-deref in engine_init_common (Nirmoy Das)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZTFDFSbd/U7YP+hI@tursulin-desk
parents 3ac5fa3f 7eeaedf7

drivers/gpu/drm/i915/gem/i915_gem_mman.c

+1 −0
Original line number Diff line number Diff line
@@ -235,6 +235,7 @@ static vm_fault_t i915_error_to_vmf_fault(int err) 
	case 0:

	case -EAGAIN:

	case -ENOSPC: /* transient failure to evict? */

	case -ENOBUFS: /* temporarily out of fences? */

	case -ERESTARTSYS:

	case -EINTR:

	case -EBUSY:

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+5 −2
Original line number Diff line number Diff line
@@ -278,7 +278,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 
		 * deals with Protected Memory which is not needed for

		 * AUX CCS invalidation and lead to unwanted side effects.

		 */

		if (mode & EMIT_FLUSH)

		if ((mode & EMIT_FLUSH) &&

		    GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70))

			bit_group_1 |= PIPE_CONTROL_FLUSH_L3;



		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
@@ -812,12 +813,14 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 
	u32 flags = (PIPE_CONTROL_CS_STALL |

		     PIPE_CONTROL_TLB_INVALIDATE |

		     PIPE_CONTROL_TILE_CACHE_FLUSH |

		     PIPE_CONTROL_FLUSH_L3 |

		     PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

		     PIPE_CONTROL_DEPTH_CACHE_FLUSH |

		     PIPE_CONTROL_DC_FLUSH_ENABLE |

		     PIPE_CONTROL_FLUSH_ENABLE);



	if (GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70))

		flags |= PIPE_CONTROL_FLUSH_L3;



	/* Wa_14016712196 */

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))

		/* dummy PIPE_CONTROL + depth flush */

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+2 −1
Original line number Diff line number Diff line
@@ -1491,6 +1491,7 @@ static int engine_init_common(struct intel_engine_cs *engine) 
	return 0;



err_bce_context:

	if (bce)

		intel_engine_destroy_pinned_context(bce);

err_ce_context:

	intel_engine_destroy_pinned_context(ce);

drivers/gpu/drm/i915/gt/intel_ggtt.c

+22 −8
Original line number Diff line number Diff line
@@ -206,24 +206,38 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt) 
	intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);

}



static void guc_ggtt_ct_invalidate(struct intel_gt *gt)

{

	struct intel_uncore *uncore = gt->uncore;

	intel_wakeref_t wakeref;



	with_intel_runtime_pm_if_active(uncore->rpm, wakeref) {

		struct intel_guc *guc = &gt->uc.guc;



		intel_guc_invalidate_tlb_guc(guc);

	}

}



static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)

{

	struct drm_i915_private *i915 = ggtt->vm.i915;

	struct intel_gt *gt;



	gen8_ggtt_invalidate(ggtt);



	if (GRAPHICS_VER(i915) >= 12) {

		struct intel_gt *gt;



		list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)

	list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) {

		if (intel_guc_tlb_invalidation_is_available(&gt->uc.guc)) {

			guc_ggtt_ct_invalidate(gt);

		} else if (GRAPHICS_VER(i915) >= 12) {

			intel_uncore_write_fw(gt->uncore,

					      GEN12_GUC_TLB_INV_CR,

					      GEN12_GUC_TLB_INV_CR_INVALIDATE);

		} else {

		intel_uncore_write_fw(ggtt->vm.gt->uncore,

			intel_uncore_write_fw(gt->uncore,

					      GEN8_GTCR, GEN8_GTCR_INVALIDATE);

		}

	}

}



static u64 mtl_ggtt_pte_encode(dma_addr_t addr,

			       unsigned int pat_index,
@@ -1243,7 +1257,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) 
		ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;

	}



	if (intel_uc_wants_guc(&ggtt->vm.gt->uc))

	if (intel_uc_wants_guc_submission(&ggtt->vm.gt->uc))

		ggtt->invalidate = guc_ggtt_invalidate;

	else

		ggtt->invalidate = gen8_ggtt_invalidate;

drivers/gpu/drm/i915/gt/intel_tlb.c

+15 −1
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include "intel_gt_print.h"

#include "intel_gt_regs.h"

#include "intel_tlb.h"

#include "uc/intel_guc.h"



/*

 * HW architecture suggest typical invalidation time at 40us,
@@ -131,11 +132,24 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno) 
		return;



	with_intel_gt_pm_if_awake(gt, wakeref) {

		struct intel_guc *guc = &gt->uc.guc;



		mutex_lock(&gt->tlb.invalidate_lock);

		if (tlb_seqno_passed(gt, seqno))

			goto unlock;



		if (HAS_GUC_TLB_INVALIDATION(gt->i915)) {

			/*

			 * Only perform GuC TLB invalidation if GuC is ready.

			 * The only time GuC could not be ready is on GT reset,

			 * which would clobber all the TLBs anyways, making

			 * any TLB invalidation path here unnecessary.

			 */

			if (intel_guc_is_ready(guc))

				intel_guc_invalidate_tlb_engines(guc);

		} else {

			mmio_invalidate_full(gt);

		}



		write_seqcount_invalidate(&gt->tlb.seqno);

unlock: