Commit 5133636e authored by Andreas Färber's avatar Andreas Färber
Browse files

arm64: dts: realtek: Add RTD1296 and Synology DS418 



Add Device Trees for RTD1296 SoC and Synology DiskStation DS418.

Cc: info@synology.com
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 1f329599

arch/arm64/boot/dts/realtek/Makefile

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Original line number Diff line number Diff line
@@ -5,3 +5,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb 
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb

dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb

dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb



dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb

arch/arm64/boot/dts/realtek/rtd1296-ds418.dts

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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)

/*

 * Copyright (c) 2017-2019 Andreas Färber

 */



/dts-v1/;



#include "rtd1296.dtsi"



/ {

	compatible = "synology,ds418", "realtek,rtd1296";

	model = "Synology DiskStation DS418";



	memory@0 {

		device_type = "memory";

		reg = <0x0 0x80000000>;

	};



	aliases {

		serial0 = &uart0;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};

};



&uart0 {

	status = "okay";

};

arch/arm64/boot/dts/realtek/rtd1296.dtsi

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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)

/*

 * Realtek RTD1296 SoC

 *

 * Copyright (c) 2017-2019 Andreas Färber

 */



#include "rtd129x.dtsi"



/ {

	compatible = "realtek,rtd1296";



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x0>;

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;

			next-level-cache = <&l2>;

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x2>;

			next-level-cache = <&l2>;

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x3>;

			next-level-cache = <&l2>;

		};



		l2: l2-cache {

			compatible = "cache";

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14

			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11

			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10

			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;

	};

};



&arm_pmu {

	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;

};