Commit 4f949033 authored by Lang Yu's avatar Lang Yu Committed by Alex Deucher
Browse files

drm/amdgpu: add PSP loading support for UMSCH 



Add front door loading support.

Signed-off-by: default avatarLang Yu <Lang.Yu@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarVeerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 40748f9a

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+9 −0
Original line number Diff line number Diff line
@@ -2399,6 +2399,15 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 
	case AMDGPU_UCODE_ID_VPE:

		*type = GFX_FW_TYPE_VPE;

		break;

	case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:

		*type = GFX_FW_TYPE_UMSCH_UCODE;

		break;

	case AMDGPU_UCODE_ID_UMSCH_MM_DATA:

		*type = GFX_FW_TYPE_UMSCH_DATA;

		break;

	case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:

		*type = GFX_FW_TYPE_UMSCH_CMD_BUFFER;

		break;

	case AMDGPU_UCODE_ID_MAXIMUM:

	default:

		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

+21 −0
Original line number Diff line number Diff line
@@ -664,6 +664,16 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) 
		return "DMCUB";

	case AMDGPU_UCODE_ID_CAP:

		return "CAP";

	case AMDGPU_UCODE_ID_VPE_CTX:

		return "VPE_CTX";

	case AMDGPU_UCODE_ID_VPE_CTL:

		return "VPE_CTL";

	case AMDGPU_UCODE_ID_VPE:

		return "VPE";

	case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:

		return "UMSCH_MM_UCODE";

	case AMDGPU_UCODE_ID_UMSCH_MM_DATA:

		return "UMSCH_MM_DATA";

	default:

		return "UNKNOWN UCODE";

	}
@@ -750,6 +760,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 
	const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;

	const struct imu_firmware_header_v1_0 *imu_hdr = NULL;

	const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;

	const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL;

	u8 *ucode_addr;



	if (!ucode->fw)
@@ -962,6 +973,16 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 
			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(vpe_hdr->ctl_ucode_offset);

			break;

		case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:

			ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes);

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(umsch_mm_hdr->header.ucode_array_offset_bytes);

			break;

		case AMDGPU_UCODE_ID_UMSCH_MM_DATA:

			ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes);

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_offset_bytes);

			break;

		default:

			ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);

			ucode_addr = (u8 *)ucode->fw->data +

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

+3 −0
Original line number Diff line number Diff line
@@ -507,6 +507,9 @@ enum AMDGPU_UCODE_ID { 
	AMDGPU_UCODE_ID_VPE_CTX,

	AMDGPU_UCODE_ID_VPE_CTL,

	AMDGPU_UCODE_ID_VPE,

	AMDGPU_UCODE_ID_UMSCH_MM_UCODE,

	AMDGPU_UCODE_ID_UMSCH_MM_DATA,

	AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,

	AMDGPU_UCODE_ID_MAXIMUM,

};

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c

+54 −0
Original line number Diff line number Diff line
@@ -76,6 +76,17 @@ struct umsch_mm_test { 
	uint32_t		num_queues;

};



int umsch_mm_psp_update_sram(struct amdgpu_device *adev, u32 ucode_size)

{

	struct amdgpu_firmware_info ucode = {

		.ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,

		.mc_addr = adev->umsch_mm.cmd_buf_gpu_addr,

		.ucode_size = ucode_size,

	};



	return psp_execute_ip_fw_load(&adev->psp, &ucode);

}



static int map_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,

			  struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,

			  uint64_t addr, uint32_t size)
@@ -600,6 +611,22 @@ int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch) 
		le32_to_cpu(umsch_mm_hdr->umsch_mm_data_start_addr_lo) |

		((uint64_t)(le32_to_cpu(umsch_mm_hdr->umsch_mm_data_start_addr_hi)) << 32);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		struct amdgpu_firmware_info *info;



		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_UMSCH_MM_UCODE];

		info->ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_UCODE;

		info->fw = adev->umsch_mm.fw;

		adev->firmware.fw_size +=

			ALIGN(le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes), PAGE_SIZE);



		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_UMSCH_MM_DATA];

		info->ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_DATA;

		info->fw = adev->umsch_mm.fw;

		adev->firmware.fw_size +=

			ALIGN(le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes), PAGE_SIZE);

	}



	return 0;

}
@@ -667,6 +694,17 @@ int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch) 
	return 0;

}



void* amdgpu_umsch_mm_add_cmd(struct amdgpu_umsch_mm *umsch,

			      void* cmd_ptr, uint32_t reg_offset, uint32_t reg_data)

{

	uint32_t* ptr = (uint32_t *)cmd_ptr;



	*ptr++ = (reg_offset << 2);

	*ptr++ = reg_data;



	return ptr;

}



static void umsch_mm_agdb_index_init(struct amdgpu_device *adev)

{

	uint32_t umsch_mm_agdb_start;
@@ -697,6 +735,17 @@ static int umsch_mm_init(struct amdgpu_device *adev) 
	adev->umsch_mm.sch_ctx_gpu_addr = adev->wb.gpu_addr +

					  (adev->umsch_mm.wb_index * 4);



	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,

				    AMDGPU_GEM_DOMAIN_GTT,

				    &adev->umsch_mm.cmd_buf_obj,

				    &adev->umsch_mm.cmd_buf_gpu_addr,

				    (void **)&adev->umsch_mm.cmd_buf_ptr);

	if (r) {

		dev_err(adev->dev, "failed to allocate cmdbuf bo %d\n", r);

		amdgpu_device_wb_free(adev, adev->umsch_mm.wb_index);

		return r;

	}



	mutex_init(&adev->umsch_mm.mutex_hidden);



	umsch_mm_agdb_index_init(adev);
@@ -760,6 +809,11 @@ static int umsch_mm_sw_fini(void *handle) 
	amdgpu_ring_fini(&adev->umsch_mm.ring);



	mutex_destroy(&adev->umsch_mm.mutex_hidden);



	amdgpu_bo_free_kernel(&adev->umsch_mm.cmd_buf_obj,

			      &adev->umsch_mm.cmd_buf_gpu_addr,

			      (void **)&adev->umsch_mm.cmd_buf_ptr);



	amdgpu_device_wb_free(adev, adev->umsch_mm.wb_index);



	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h

+8 −0
Original line number Diff line number Diff line
@@ -147,6 +147,10 @@ struct amdgpu_umsch_mm { 
	uint64_t			data_start_addr;

	uint32_t			data_size;



	struct amdgpu_bo		*cmd_buf_obj;

	uint64_t			cmd_buf_gpu_addr;

	uint32_t			*cmd_buf_ptr;



	uint32_t			wb_index;

	uint64_t			sch_ctx_gpu_addr;

	uint32_t			*sch_ctx_cpu_addr;
@@ -163,12 +167,16 @@ struct amdgpu_umsch_mm { 
	struct mutex			mutex_hidden;

};



int umsch_mm_psp_update_sram(struct amdgpu_device *adev, u32 ucode_size);



int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws);

int amdgpu_umsch_mm_query_fence(struct amdgpu_umsch_mm *umsch);



int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch);

int amdgpu_umsch_mm_allocate_ucode_buffer(struct amdgpu_umsch_mm *umsch);

int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch);

void* amdgpu_umsch_mm_add_cmd(struct amdgpu_umsch_mm *umsch,

			      void* cmd_ptr, uint32_t reg_offset, uint32_t reg_data);



int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch);