Commit 4bdb00ed authored by Enric Balletbo i Serra's avatar Enric Balletbo i Serra Committed by Matthias Brugger
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arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0 



Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.

While here, also remove the undocumented and also not used
'mediatek,syscon-dsi' property.

Signed-off-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210930103105.v4.5.I933f1532d7a1b2910843a9644c86a7d94a4b44e1@changeid


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 7fdb1bc3

arch/arm64/boot/dts/mediatek/mt8183.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -1319,6 +1319,7 @@ mmsys: syscon@14000000 { 
			compatible = "mediatek,mt8183-mmsys", "syscon";

			reg = <0 0x14000000 0 0x1000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,

				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;

			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@@ -1433,11 +1434,11 @@ dsi0: dsi@14014000 { 
			reg = <0 0x14014000 0 0x1000>;

			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;

			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;

			mediatek,syscon-dsi = <&mmsys 0x140>;

			clocks = <&mmsys CLK_MM_DSI0_MM>,

				 <&mmsys CLK_MM_DSI0_IF>,

				 <&mipi_tx0>;

			clock-names = "engine", "digital", "hs";

			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;

			phys = <&mipi_tx0>;

			phy-names = "dphy";

		};

include/dt-bindings/reset/mt8183-resets.h

+3 −0
Original line number Diff line number Diff line
@@ -80,6 +80,9 @@ 


#define MT8183_INFRACFG_SW_RST_NUM				128



/* MMSYS resets */

#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0			25



#define MT8183_TOPRGU_MM_SW_RST					1

#define MT8183_TOPRGU_MFG_SW_RST				2

#define MT8183_TOPRGU_VENC_SW_RST				3