Commit 4bd7bfb4 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Bjorn Andersson
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ARM: dts: qcom: sdx55: Add QPIC NAND support 



Add qpic_nand node to support QPIC NAND controller on SDX55 platform.
Since there is no "aon" clock in SDX55, a dummy clock is provided.

Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210106125322.61840-11-manivannan.sadhasivam@linaro.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 24709418

arch/arm/boot/dts/qcom-sdx55.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -35,6 +35,12 @@ sleep_clk: sleep-clk { 
			#clock-cells = <0>;

			clock-frequency = <32000>;

		};



		nand_clk_dummy: nand-clk-dummy {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32000>;

		};

	};



	cpus {
@@ -149,6 +155,22 @@ qpic_bam: dma-controller@1b04000 { 
			status = "disabled";

		};



		qpic_nand: nand@1b30000 {

			compatible = "qcom,sdx55-nand";

			reg = <0x01b30000 0x10000>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&rpmhcc RPMH_QPIC_CLK>,

				 <&nand_clk_dummy>;

			clock-names = "core", "aon";



			dmas = <&qpic_bam 0>,

			       <&qpic_bam 1>,

			       <&qpic_bam 2>;

			dma-names = "tx", "rx", "cmd";

			status = "disabled";

		};



		tcsr_mutex: hwlock@1f40000 {

			compatible = "qcom,tcsr-mutex";

			reg = <0x01f40000 0x40000>;