Commit 49f2a554 authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman
Browse files

staging: r8188eu: Remove wrapper rtw_udelay_os() 



This wrapper is a simple call to udelay(). Remove it.

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Link: https://lore.kernel.org/r/20210805192644.15978-4-Larry.Finger@lwfinger.net


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e72e1495

drivers/staging/r8188eu/core/rtw_efuse.c

+1 −1
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ ReadEFuseByte( 
	/*  This fix the problem that Efuse read error in high temperature condition. */

	/*  Designer says that there shall be some delay after ready bit is set, or the */

	/*  result will always stay on last data we read. */

	rtw_udelay_os(50);

	udelay(50);

	value32 = rtw_read32(Adapter, EFUSE_CTRL);



	*pbuf = (u8)(value32 & 0xff);

drivers/staging/r8188eu/hal/HalPwrSeqCmd.c

+3 −3
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, 
					if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)))

						poll_bit = true;

					else

						rtw_udelay_os(10);

						udelay(10);



					if (poll_count++ > max_poll_count) {

						DBG_88E("Fail to polling Offset[%#x]\n", offset);
@@ -76,9 +76,9 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, 
				break;

			case PWR_CMD_DELAY:

				if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)

					rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd));

					udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd));

				else

					rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);

					udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);

				break;

			case PWR_CMD_END:

				/*  When this command is parsed, end the process */

drivers/staging/r8188eu/hal/odm_interface.c

+2 −2
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ void ODM_IsWorkItemScheduled(void *pRtWorkItem) 
/*  ODM Timer relative API. */

void ODM_StallExecution(u32 usDelay)

{

	rtw_udelay_os(usDelay);

	udelay(usDelay);

}



void ODM_delay_ms(u32 ms)
@@ -142,7 +142,7 @@ void ODM_delay_ms(u32 ms) 


void ODM_delay_us(u32 us)

{

	rtw_udelay_os(us);

	udelay(us);

}



void ODM_sleep_ms(u32 ms)

drivers/staging/r8188eu/hal/rtl8188e_hal_init.c

+1 −1
Original line number Diff line number Diff line
@@ -533,7 +533,7 @@ static s32 _FWFreeToGo(struct adapter *padapter) 
			DBG_88E("%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n", __func__, value32);

			return _SUCCESS;

		}

		rtw_udelay_os(5);

		udelay(5);

	} while (counter++ < POLLING_READY_TIMEOUT_COUNT);



	DBG_88E("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __func__, value32);

drivers/staging/r8188eu/hal/rtl8188e_phycfg.c

+3 −3
Original line number Diff line number Diff line
@@ -170,12 +170,12 @@ phy_RFSerialRead( 
	tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;	/* T65 RF */



	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));

	rtw_udelay_os(10);/*  PlatformStallExecution(10); */

	udelay(10);/*  PlatformStallExecution(10); */



	PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);

	rtw_udelay_os(100);/* PlatformStallExecution(100); */

	udelay(100);/* PlatformStallExecution(100); */



	rtw_udelay_os(10);/* PlatformStallExecution(10); */

	udelay(10);/* PlatformStallExecution(10); */



	if (eRFPath == RF_PATH_A)

		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);