Commit 47659738 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: allocate doorbell index for multi-die case



Allocate different doorbell index for kiq/kcq rings
on each die

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 47fc644f
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+8 −1
Original line number Diff line number Diff line
@@ -83,6 +83,8 @@ struct amdgpu_doorbell_index {
	};
	uint32_t first_non_cp;
	uint32_t last_non_cp;
	uint32_t xcc1_kiq_start;
	uint32_t xcc1_mec_ring0_start;
	uint32_t max_assignment;
	/* Per engine SDMA doorbell size in dword */
	uint32_t sdma_doorbell_range;
@@ -164,7 +166,12 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
	AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP            = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
	AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP             = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,

	AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x18F,
	/* kiq/kcq from second XCD. Max 8 XCDs */
	AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START             = 0x190,
	/* 8 compute rings per GC. Max to 0x1CE */
	AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START       = 0x197,

	AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x1CE,
	AMDGPU_VEGA20_DOORBELL_INVALID                   = 0xFFFF
} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;

+5 −0
Original line number Diff line number Diff line
@@ -316,6 +316,11 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
	ring->doorbell_index = adev->doorbell_index.kiq;
	ring->xcc_id = xcc_id;
	ring->vm_hub = AMDGPU_GFXHUB_0;
	if (xcc_id >= 1)
		ring->doorbell_index = adev->doorbell_index.xcc1_kiq_start +
					xcc_id - 1;
	else
		ring->doorbell_index = adev->doorbell_index.kiq;

	r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id);
	if (r)
+1 −0
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@@ -270,6 +270,7 @@ void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
	entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
	entry->timestamp_src = dw[2] >> 31;
	entry->pasid = dw[3] & 0xffff;
	entry->node_id = (dw[3] >> 16) & 0xff;
	entry->pasid_src = dw[3] >> 31;
	entry->src_data[0] = dw[4];
	entry->src_data[1] = dw[5];
+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ struct amdgpu_iv_entry {
	uint64_t timestamp;
	unsigned timestamp_src;
	unsigned pasid;
	unsigned node_id;
	unsigned pasid_src;
	unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
	const uint32_t *iv_entry;
+7 −1
Original line number Diff line number Diff line
@@ -752,7 +752,13 @@ static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,

	ring->ring_obj = NULL;
	ring->use_doorbell = true;
	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
	if (xcc_id >= 1)
		ring->doorbell_index =
				(adev->doorbell_index.xcc1_mec_ring0_start +
				ring_id - adev->gfx.num_compute_rings) << 1;
	else
		ring->doorbell_index =
				(adev->doorbell_index.mec_ring0 + ring_id) << 1;
	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
				+ (ring_id * GFX9_MEC_HPD_SIZE);
	ring->vm_hub = AMDGPU_GFXHUB_0;