Commit 44dd5e21 authored by Cameron Nemo's avatar Cameron Nemo Committed by Heiko Stuebner
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arm64: dts: rockchip: add rk3328 dwc3 usb controller node 



RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.

Signed-off-by: default avatarWilliam Wu <william.wu@rock-chips.com>
Signed-off-by: default avatarCameron Nemo <cnemo@tutanota.com>
Signed-off-by: default avatarJohan Jonker <jbx6244@gmail.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210209192350.7130-7-jbx6244@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent db792e9a

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -980,6 +980,25 @@ usb_host0_ohci: usb@ff5d0000 { 
		status = "disabled";

	};



	usbdrd3: usb@ff600000 {

		compatible = "rockchip,rk3328-dwc3", "snps,dwc3";

		reg = <0x0 0xff600000 0x0 0x100000>;

		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,

			 <&cru ACLK_USB3OTG>;

		clock-names = "ref_clk", "suspend_clk",

			      "bus_clk";

		dr_mode = "otg";

		phy_type = "utmi_wide";

		snps,dis-del-phy-power-chg-quirk;

		snps,dis_enblslpm_quirk;

		snps,dis-tx-ipgap-linecheck-quirk;

		snps,dis-u2-freeclk-exists-quirk;

		snps,dis_u2_susphy_quirk;

		snps,dis_u3_susphy_quirk;

		status = "disabled";

	};



	gic: interrupt-controller@ff811000 {

		compatible = "arm,gic-400";

		#interrupt-cells = <3>;