Commit 4387b104 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: add more members for dpm table 



These members can help to cache the clock frequencies for all
dpm levels. Then simplifying the code for dpm level switching
is possible.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 273da6ff

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+13 −2
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ 


#define SMU11_TOOL_SIZE			0x19000



#define MAX_DPM_LEVELS 16

#define MAX_PCIE_CONF 2



#define CLK_MAP(clk, index) \
@@ -91,9 +92,17 @@ struct smu_11_0_max_sustainable_clocks { 
	uint32_t soc_clock;

};



struct smu_11_0_dpm_clk_level {

	bool				enabled;

	uint32_t			value;

};



struct smu_11_0_dpm_table {

	uint32_t			min;        /* MHz */

	uint32_t			max;        /* MHz */

	uint32_t			count;

	bool				is_fine_grained;

	struct smu_11_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];

};



struct smu_11_0_pcie_table {
@@ -107,7 +116,9 @@ struct smu_11_0_dpm_tables { 
	struct smu_11_0_dpm_table        uclk_table;

	struct smu_11_0_dpm_table        eclk_table;

	struct smu_11_0_dpm_table        vclk_table;

	struct smu_11_0_dpm_table        vclk1_table;

	struct smu_11_0_dpm_table        dclk_table;

	struct smu_11_0_dpm_table        dclk1_table;

	struct smu_11_0_dpm_table        dcef_table;

	struct smu_11_0_dpm_table        pixel_table;

	struct smu_11_0_dpm_table        display_table;