Commit 410c756d authored by Mike Rapoport's avatar Mike Rapoport Committed by Greg Kroah-Hartman
Browse files

staging: sm750fb: use BIT macro for SYSTEM_CTRL single-bit fields 



Replace complex definition of SYSTEM_CTRL fields and usage of
FIELD_GET/SET with BIT() macro and open-coded register value modifications

Signed-off-by: default avatarMike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1c3ad306

drivers/staging/sm750fb/ddk750_display.c

+8 −16
Original line number Diff line number Diff line
@@ -136,17 +136,13 @@ static void waitNextVerticalSync(int ctrl, int delay) 
		while (delay-- > 0) {

			/* Wait for end of vsync. */

			do {

				status = FIELD_GET(PEEK32(SYSTEM_CTRL),

						   SYSTEM_CTRL,

						   PANEL_VSYNC);

			} while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);

				status = PEEK32(SYSTEM_CTRL);

			} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);



			/* Wait for start of vsync. */

			do {

				status = FIELD_GET(PEEK32(SYSTEM_CTRL),

						   SYSTEM_CTRL,

						   PANEL_VSYNC);

			} while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE);

				status = PEEK32(SYSTEM_CTRL);

			} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));

		}



	} else {
@@ -163,17 +159,13 @@ static void waitNextVerticalSync(int ctrl, int delay) 
		while (delay-- > 0) {

			/* Wait for end of vsync. */

			do {

				status = FIELD_GET(PEEK32(SYSTEM_CTRL),

								   SYSTEM_CTRL,

								   CRT_VSYNC);

			} while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE);

				status = PEEK32(SYSTEM_CTRL);

			} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);



			/* Wait for start of vsync. */

			do {

				status = FIELD_GET(PEEK32(SYSTEM_CTRL),

								   SYSTEM_CTRL,

								   CRT_VSYNC);

			} while (status == SYSTEM_CTRL_CRT_VSYNC_INACTIVE);

				status = PEEK32(SYSTEM_CTRL);

			} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));

		}

	}

}

drivers/staging/sm750fb/ddk750_reg.h

+19 −57
Original line number Diff line number Diff line
@@ -16,68 +16,30 @@ 
#define SYSTEM_CTRL_DPMS_VPHN                         1

#define SYSTEM_CTRL_DPMS_VNHP                         2

#define SYSTEM_CTRL_DPMS_VNHN                         3

#define SYSTEM_CTRL_PCI_BURST                         29:29

#define SYSTEM_CTRL_PCI_BURST_OFF                     0

#define SYSTEM_CTRL_PCI_BURST_ON                      1

#define SYSTEM_CTRL_PCI_MASTER                        25:25

#define SYSTEM_CTRL_PCI_MASTER_OFF                    0

#define SYSTEM_CTRL_PCI_MASTER_ON                     1

#define SYSTEM_CTRL_LATENCY_TIMER                     24:24

#define SYSTEM_CTRL_LATENCY_TIMER_ON                  0

#define SYSTEM_CTRL_LATENCY_TIMER_OFF                 1

#define SYSTEM_CTRL_DE_FIFO                           23:23

#define SYSTEM_CTRL_DE_FIFO_NOTEMPTY                  0

#define SYSTEM_CTRL_DE_FIFO_EMPTY                     1

#define SYSTEM_CTRL_DE_STATUS                         22:22

#define SYSTEM_CTRL_DE_STATUS_IDLE                    0

#define SYSTEM_CTRL_DE_STATUS_BUSY                    1

#define SYSTEM_CTRL_DE_MEM_FIFO                       21:21

#define SYSTEM_CTRL_DE_MEM_FIFO_NOTEMPTY              0

#define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY                 1

#define SYSTEM_CTRL_CSC_STATUS                        20:20

#define SYSTEM_CTRL_CSC_STATUS_IDLE                   0

#define SYSTEM_CTRL_CSC_STATUS_BUSY                   1

#define SYSTEM_CTRL_CRT_VSYNC                         19:19

#define SYSTEM_CTRL_CRT_VSYNC_INACTIVE                0

#define SYSTEM_CTRL_CRT_VSYNC_ACTIVE                  1

#define SYSTEM_CTRL_PANEL_VSYNC                       18:18

#define SYSTEM_CTRL_PANEL_VSYNC_INACTIVE              0

#define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE                1

#define SYSTEM_CTRL_CURRENT_BUFFER                    17:17

#define SYSTEM_CTRL_CURRENT_BUFFER_NORMAL             0

#define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING       1

#define SYSTEM_CTRL_DMA_STATUS                        16:16

#define SYSTEM_CTRL_DMA_STATUS_IDLE                   0

#define SYSTEM_CTRL_DMA_STATUS_BUSY                   1

#define SYSTEM_CTRL_PCI_BURST_READ                    15:15

#define SYSTEM_CTRL_PCI_BURST_READ_OFF                0

#define SYSTEM_CTRL_PCI_BURST_READ_ON                 1

#define SYSTEM_CTRL_DE_ABORT                          13:13

#define SYSTEM_CTRL_DE_ABORT_OFF                      0

#define SYSTEM_CTRL_DE_ABORT_ON                       1

#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK                11:11

#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK_OFF            0

#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK_ON             1

#define SYSTEM_CTRL_PCI_RETRY                         7:7

#define SYSTEM_CTRL_PCI_RETRY_ON                      0

#define SYSTEM_CTRL_PCI_RETRY_OFF                     1

#define SYSTEM_CTRL_PCI_BURST                         BIT(29)

#define SYSTEM_CTRL_PCI_MASTER                        BIT(25)

#define SYSTEM_CTRL_LATENCY_TIMER_OFF                 BIT(24)

#define SYSTEM_CTRL_DE_FIFO_EMPTY                     BIT(23)

#define SYSTEM_CTRL_DE_STATUS_BUSY                    BIT(22)

#define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY                 BIT(21)

#define SYSTEM_CTRL_CSC_STATUS_BUSY                   BIT(20)

#define SYSTEM_CTRL_CRT_VSYNC_ACTIVE                  BIT(19)

#define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE                BIT(18)

#define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING       BIT(17)

#define SYSTEM_CTRL_DMA_STATUS_BUSY                   BIT(16)

#define SYSTEM_CTRL_PCI_BURST_READ                    BIT(15)

#define SYSTEM_CTRL_DE_ABORT                          BIT(13)

#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK                BIT(11)

#define SYSTEM_CTRL_PCI_RETRY_OFF                     BIT(7)

#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE         5:4

#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1       0

#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2       1

#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4       2

#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8       3

#define SYSTEM_CTRL_CRT_TRISTATE                      3:3

#define SYSTEM_CTRL_CRT_TRISTATE_OFF                  0

#define SYSTEM_CTRL_CRT_TRISTATE_ON                   1

#define SYSTEM_CTRL_PCIMEM_TRISTATE                   2:2

#define SYSTEM_CTRL_PCIMEM_TRISTATE_OFF               0

#define SYSTEM_CTRL_PCIMEM_TRISTATE_ON                1

#define SYSTEM_CTRL_LOCALMEM_TRISTATE                 1:1

#define SYSTEM_CTRL_LOCALMEM_TRISTATE_OFF             0

#define SYSTEM_CTRL_LOCALMEM_TRISTATE_ON              1

#define SYSTEM_CTRL_PANEL_TRISTATE                    0:0

#define SYSTEM_CTRL_PANEL_TRISTATE_OFF                0

#define SYSTEM_CTRL_PANEL_TRISTATE_ON                 1

#define SYSTEM_CTRL_CRT_TRISTATE                      BIT(3)

#define SYSTEM_CTRL_PCIMEM_TRISTATE                   BIT(2)

#define SYSTEM_CTRL_LOCALMEM_TRISTATE                 BIT(1)

#define SYSTEM_CTRL_PANEL_TRISTATE                    BIT(0)



#define MISC_CTRL                                     0x000004

#define MISC_CTRL_DRAM_RERESH_COUNT                   27:27

drivers/staging/sm750fb/sm750_hw.c

+8 −7
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev) 
	/* for sm718,open pci burst */

	if (sm750_dev->devid == 0x718) {

		POKE32(SYSTEM_CTRL,

				FIELD_SET(PEEK32(SYSTEM_CTRL), SYSTEM_CTRL, PCI_BURST, ON));

		       PEEK32(SYSTEM_CTRL) | SYSTEM_CTRL_PCI_BURST);

	}



	if (getChipType() != SM750LE) {
@@ -478,11 +478,11 @@ void hw_sm750_initAccel(struct sm750_dev *sm750_dev) 
	} else {

		/* engine reset */

		reg = PEEK32(SYSTEM_CTRL);

	    reg = FIELD_SET(reg, SYSTEM_CTRL, DE_ABORT, ON);

		reg |= SYSTEM_CTRL_DE_ABORT;

		POKE32(SYSTEM_CTRL, reg);



		reg = PEEK32(SYSTEM_CTRL);

		reg = FIELD_SET(reg, SYSTEM_CTRL, DE_ABORT, OFF);

		reg &= ~SYSTEM_CTRL_DE_ABORT;

		POKE32(SYSTEM_CTRL, reg);

	}
@@ -511,16 +511,17 @@ int hw_sm750le_deWait(void) 
int hw_sm750_deWait(void)

{

	int i = 0x10000000;

	unsigned int mask = SYSTEM_CTRL_DE_STATUS_BUSY |

		SYSTEM_CTRL_DE_FIFO_EMPTY |

		SYSTEM_CTRL_DE_MEM_FIFO_EMPTY;



	while (i--) {

		unsigned int val = PEEK32(SYSTEM_CTRL);



		if ((FIELD_GET(val, SYSTEM_CTRL, DE_STATUS) == SYSTEM_CTRL_DE_STATUS_IDLE) &&

		    (FIELD_GET(val, SYSTEM_CTRL, DE_FIFO) == SYSTEM_CTRL_DE_FIFO_EMPTY) &&

		    (FIELD_GET(val, SYSTEM_CTRL, DE_MEM_FIFO) == SYSTEM_CTRL_DE_MEM_FIFO_EMPTY)) {

		if ((val & mask) ==

		    (SYSTEM_CTRL_DE_FIFO_EMPTY | SYSTEM_CTRL_DE_MEM_FIFO_EMPTY))

			return 0;

	}

	}

	/* timeout error */

	return -1;

}