Commit 3f942817 authored by Kent Russell's avatar Kent Russell Committed by Alex Deucher
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drm/amdgpu: Add SMUIO values for other I2C controller v2 



These are the offsets for CKSVII2C1, and match up with the values
already added for CKSVII2C

v2: Don't remove some of the CSKVII2C values

Signed-off-by: default avatarKent Russell <kent.russell@amd.com>
Reviewed-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b55a8b8b

drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h

+92 −0
Original line number Diff line number Diff line
@@ -121,6 +121,98 @@ 
#define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX                                                            0

#define mmCKSVII2C_IC_COMP_TYPE                                                                        0x006d

#define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX                                                               0

#define mmCKSVII2C1_IC_CON                                                                             0x0080

#define mmCKSVII2C1_IC_CON_BASE_IDX                                                                    0

#define mmCKSVII2C1_IC_TAR                                                                             0x0081

#define mmCKSVII2C1_IC_TAR_BASE_IDX                                                                    0

#define mmCKSVII2C1_IC_SAR                                                                             0x0082

#define mmCKSVII2C1_IC_SAR_BASE_IDX                                                                    0

#define mmCKSVII2C1_IC_HS_MADDR                                                                        0x0083

#define mmCKSVII2C1_IC_HS_MADDR_BASE_IDX                                                               0

#define mmCKSVII2C1_IC_DATA_CMD                                                                        0x0084

#define mmCKSVII2C1_IC_DATA_CMD_BASE_IDX                                                               0

#define mmCKSVII2C1_IC_SS_SCL_HCNT                                                                     0x0085

#define mmCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_SS_SCL_LCNT                                                                     0x0086

#define mmCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_FS_SCL_HCNT                                                                     0x0087

#define mmCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_FS_SCL_LCNT                                                                     0x0088

#define mmCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_HS_SCL_HCNT                                                                     0x0089

#define mmCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_HS_SCL_LCNT                                                                     0x008a

#define mmCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_INTR_STAT                                                                       0x008b

#define mmCKSVII2C1_IC_INTR_STAT_BASE_IDX                                                              0

#define mmCKSVII2C1_IC_INTR_MASK                                                                       0x008c

#define mmCKSVII2C1_IC_INTR_MASK_BASE_IDX                                                              0

#define mmCKSVII2C1_IC_RAW_INTR_STAT                                                                   0x008d

#define mmCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX                                                          0

#define mmCKSVII2C1_IC_RX_TL                                                                           0x008e

#define mmCKSVII2C1_IC_RX_TL_BASE_IDX                                                                  0

#define mmCKSVII2C1_IC_TX_TL                                                                           0x008f

#define mmCKSVII2C1_IC_TX_TL_BASE_IDX                                                                  0

#define mmCKSVII2C1_IC_CLR_INTR                                                                        0x0090

#define mmCKSVII2C1_IC_CLR_INTR_BASE_IDX                                                               0

#define mmCKSVII2C1_IC_CLR_RX_UNDER                                                                    0x0091

#define mmCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX                                                           0

#define mmCKSVII2C1_IC_CLR_RX_OVER                                                                     0x0092

#define mmCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_CLR_TX_OVER                                                                     0x0093

#define mmCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_CLR_RD_REQ                                                                      0x0094

#define mmCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX                                                             0

#define mmCKSVII2C1_IC_CLR_TX_ABRT                                                                     0x0095

#define mmCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_CLR_RX_DONE                                                                     0x0096

#define mmCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX                                                            0

#define mmCKSVII2C1_IC_CLR_ACTIVITY                                                                    0x0097

#define mmCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX                                                           0

#define mmCKSVII2C1_IC_CLR_STOP_DET                                                                    0x0098

#define mmCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX                                                           0

#define mmCKSVII2C1_IC_CLR_START_DET                                                                   0x0099

#define mmCKSVII2C1_IC_CLR_START_DET_BASE_IDX                                                          0

#define mmCKSVII2C1_IC_CLR_GEN_CALL                                                                    0x009a

#define mmCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX                                                           0

#define mmCKSVII2C1_IC_ENABLE                                                                          0x009b

#define mmCKSVII2C1_IC_ENABLE_BASE_IDX                                                                 0

#define mmCKSVII2C1_IC_STATUS                                                                          0x009c

#define mmCKSVII2C1_IC_STATUS_BASE_IDX                                                                 0

#define mmCKSVII2C1_IC_TXFLR                                                                           0x009d

#define mmCKSVII2C1_IC_TXFLR_BASE_IDX                                                                  0

#define mmCKSVII2C1_IC_RXFLR                                                                           0x009e

#define mmCKSVII2C1_IC_RXFLR_BASE_IDX                                                                  0

#define mmCKSVII2C1_IC_SDA_HOLD                                                                        0x009f

#define mmCKSVII2C1_IC_SDA_HOLD_BASE_IDX                                                               0

#define mmCKSVII2C1_IC_TX_ABRT_SOURCE                                                                  0x00a0

#define mmCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX                                                         0

#define mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY                                                              0x00a1

#define mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX                                                     0

#define mmCKSVII2C1_IC_DMA_CR                                                                          0x00a2

#define mmCKSVII2C1_IC_DMA_CR_BASE_IDX                                                                 0

#define mmCKSVII2C1_IC_DMA_TDLR                                                                        0x00a3

#define mmCKSVII2C1_IC_DMA_TDLR_BASE_IDX                                                               0

#define mmCKSVII2C1_IC_DMA_RDLR                                                                        0x00a4

#define mmCKSVII2C1_IC_DMA_RDLR_BASE_IDX                                                               0

#define mmCKSVII2C1_IC_SDA_SETUP                                                                       0x00a5

#define mmCKSVII2C1_IC_SDA_SETUP_BASE_IDX                                                              0

#define mmCKSVII2C1_IC_ACK_GENERAL_CALL                                                                0x00a6

#define mmCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX                                                       0

#define mmCKSVII2C1_IC_ENABLE_STATUS                                                                   0x00a7

#define mmCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX                                                          0

#define mmCKSVII2C1_IC_FS_SPKLEN                                                                       0x00a8

#define mmCKSVII2C1_IC_FS_SPKLEN_BASE_IDX                                                              0

#define mmCKSVII2C1_IC_HS_SPKLEN                                                                       0x00a9

#define mmCKSVII2C1_IC_HS_SPKLEN_BASE_IDX                                                              0

#define mmCKSVII2C1_IC_CLR_RESTART_DET                                                                 0x00aa

#define mmCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX                                                        0

#define mmCKSVII2C1_IC_COMP_PARAM_1                                                                    0x00ab

#define mmCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX                                                           0

#define mmCKSVII2C1_IC_COMP_VERSION                                                                    0x00ac

#define mmCKSVII2C1_IC_COMP_VERSION_BASE_IDX                                                           0

#define mmCKSVII2C1_IC_COMP_TYPE                                                                       0x00ad

#define mmCKSVII2C1_IC_COMP_TYPE_BASE_IDX                                                              0

#define mmSMUIO_MP_RESET_INTR                                                                          0x00c1

#define mmSMUIO_MP_RESET_INTR_BASE_IDX                                                                 0

#define mmSMUIO_SOC_HALT                                                                               0x00c2

drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h

+176 −0

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