Commit 3ce22442 authored by Jun Lei's avatar Jun Lei Committed by Alex Deucher
Browse files

drm/amd/display: clear underflow on optc unblank 



[why]
Underflow is asserted due to some timing condition which does not
actually result in visible underflow (i.e. it occurs while blanked).

[how]
Force clear underflow occured bit whenver we unblank.

Signed-off-by: default avatarJun Lei <Jun.Lei@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6263f0fd

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+9 −10
Original line number Diff line number Diff line
@@ -359,20 +359,19 @@ void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enab 
static void optc1_unblank_crtc(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);

	uint32_t vertical_interrupt_enable = 0;



	REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,

			OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &vertical_interrupt_enable);



	/* temporary work around for vertical interrupt, once vertical interrupt enabled,

	 * this check will be removed.

	 */

	if (vertical_interrupt_enable)

		optc1_set_blank_data_double_buffer(optc, true);



	REG_UPDATE_2(OTG_BLANK_CONTROL,

			OTG_BLANK_DATA_EN, 0,

			OTG_BLANK_DE_MODE, 0);



	/* W/A for automated testing

	 * Automated testing will fail underflow test as there

	 * sporadic underflows which occur during the optc blank

	 * sequence.  As a w/a, clear underflow on unblank.

	 * This prevents the failure, but will not mask actual

	 * underflow that affect real use cases.

	 */

	optc1_clear_optc_underflow(optc);

}



/**