Commit 3b8b44a4 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add debug option to bypass ssinfo from bios for dcn315 



[Why & How]
Add debug option to bypass ssinfo from BIOS for dcn315.

Reviewed-by: default avatarPark, Chris <Chris.Park@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7c916f95

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+4 −1
Original line number Diff line number Diff line
@@ -526,6 +526,7 @@ void dcn315_clk_mgr_construct( 
		struct dccg *dccg)

{

	struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };

	struct clk_mgr *clk_mgr_base = ctx->dc->clk_mgr;



	clk_mgr->base.base.ctx = ctx;

	clk_mgr->base.base.funcs = &dcn315_funcs;
@@ -586,8 +587,10 @@ void dcn315_clk_mgr_construct( 
	}



	clk_mgr->base.base.dprefclk_khz = 600000;

	clk_mgr->base.dccg->ref_dtbclk_khz = 600000;

	clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);

	clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

	dce_clock_read_ss_info(&clk_mgr->base);

	clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);



	clk_mgr->base.base.bw_params = &dcn315_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

+24 −0
Original line number Diff line number Diff line
@@ -312,3 +312,27 @@ void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) 
			VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);

}



int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)

{

	int dprefclk_get_mhz = -1;

	if (clk_mgr->smu_present) {

		dprefclk_get_mhz = dcn315_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_GetDprefclkFreq,

			0);

	}

	return (dprefclk_get_mhz * 1000);

}



int dcn315_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr)

{

	int fclk_get_mhz = -1;



	if (clk_mgr->smu_present) {

		fclk_get_mhz = dcn315_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_GetFclkFrequency,

			0);

	}

	return (fclk_get_mhz * 1000);

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

+2 −0
Original line number Diff line number Diff line
@@ -123,4 +123,6 @@ void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); 
void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

void dcn315_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);

void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);

int dcn315_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr);

#endif /* DAL_DC_315_SMU_H_ */

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

+2 −0
Original line number Diff line number Diff line
@@ -450,6 +450,8 @@ void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce) 
				clk_mgr_dce->dprefclk_ss_percentage =

						info.spread_spectrum_percentage;

			}

			if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)

				clk_mgr_dce->dprefclk_ss_percentage = 0;

		}

	}

}