Commit 3b17c8f9 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'timers-v5.10' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 

Pull clocksource/event updates from Daniel Lezcano:

 - Add DT binding documentation to support the r8a7742 and r8a774e1
   platforms (Lad Prabhakar)

 - Add sp804 variant support for the Hisilicon platforms (Kefeng Wang)
parents b952caf2 549437a4

Documentation/devicetree/bindings/timer/renesas,cmt.yaml

+4 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ properties: 
      - items:

          - enum:

              - renesas,r8a73a4-cmt0      # 32-bit CMT0 on R-Mobile APE6

              - renesas,r8a7742-cmt0      # 32-bit CMT0 on RZ/G1H

              - renesas,r8a7743-cmt0      # 32-bit CMT0 on RZ/G1M

              - renesas,r8a7744-cmt0      # 32-bit CMT0 on RZ/G1N

              - renesas,r8a7745-cmt0      # 32-bit CMT0 on RZ/G1E
@@ -53,6 +54,7 @@ properties: 
      - items:

          - enum:

              - renesas,r8a73a4-cmt1      # 48-bit CMT1 on R-Mobile APE6

              - renesas,r8a7742-cmt1      # 48-bit CMT1 on RZ/G1H

              - renesas,r8a7743-cmt1      # 48-bit CMT1 on RZ/G1M

              - renesas,r8a7744-cmt1      # 48-bit CMT1 on RZ/G1N

              - renesas,r8a7745-cmt1      # 48-bit CMT1 on RZ/G1E
@@ -69,6 +71,7 @@ properties: 
              - renesas,r8a774a1-cmt0     # 32-bit CMT0 on RZ/G2M

              - renesas,r8a774b1-cmt0     # 32-bit CMT0 on RZ/G2N

              - renesas,r8a774c0-cmt0     # 32-bit CMT0 on RZ/G2E

              - renesas,r8a774e1-cmt0     # 32-bit CMT0 on RZ/G2H

              - renesas,r8a7795-cmt0      # 32-bit CMT0 on R-Car H3

              - renesas,r8a7796-cmt0      # 32-bit CMT0 on R-Car M3-W

              - renesas,r8a77965-cmt0     # 32-bit CMT0 on R-Car M3-N
@@ -83,6 +86,7 @@ properties: 
              - renesas,r8a774a1-cmt1     # 48-bit CMT on RZ/G2M

              - renesas,r8a774b1-cmt1     # 48-bit CMT on RZ/G2N

              - renesas,r8a774c0-cmt1     # 48-bit CMT on RZ/G2E

              - renesas,r8a774e1-cmt1     # 48-bit CMT on RZ/G2H

              - renesas,r8a7795-cmt1      # 48-bit CMT on R-Car H3

              - renesas,r8a7796-cmt1      # 48-bit CMT on R-Car M3-W

              - renesas,r8a77965-cmt1     # 48-bit CMT on R-Car M3-N

drivers/clocksource/timer-sp.h

+32 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
 *

 * Every SP804 contains two identical timers.

 */

#define NR_TIMERS	2

#define TIMER_1_BASE	0x00

#define TIMER_2_BASE	0x20
@@ -29,3 +30,34 @@ 
#define TIMER_RIS	0x10			/*  CVR ro */

#define TIMER_MIS	0x14			/*  CVR ro */

#define TIMER_BGLOAD	0x18			/*  CVR rw */



struct sp804_timer {

	int load;

	int load_h;

	int value;

	int value_h;

	int ctrl;

	int intclr;

	int ris;

	int mis;

	int bgload;

	int bgload_h;

	int timer_base[NR_TIMERS];

	int width;

};



struct sp804_clkevt {

	void __iomem *base;

	void __iomem *load;

	void __iomem *load_h;

	void __iomem *value;

	void __iomem *value_h;

	void __iomem *ctrl;

	void __iomem *intclr;

	void __iomem *ris;

	void __iomem *mis;

	void __iomem *bgload;

	void __iomem *bgload_h;

	unsigned long reload;

	int width;

};

drivers/clocksource/timer-sp804.c

+147 −63
Original line number Diff line number Diff line
@@ -18,15 +18,57 @@ 
#include <linux/of_irq.h>

#include <linux/sched_clock.h>



#include <clocksource/timer-sp804.h>



#include "timer-sp.h"



static long __init sp804_get_clock_rate(struct clk *clk)

/* Hisilicon 64-bit timer(a variant of ARM SP804) */

#define HISI_TIMER_1_BASE	0x00

#define HISI_TIMER_2_BASE	0x40

#define HISI_TIMER_LOAD		0x00

#define HISI_TIMER_LOAD_H	0x04

#define HISI_TIMER_VALUE	0x08

#define HISI_TIMER_VALUE_H	0x0c

#define HISI_TIMER_CTRL		0x10

#define HISI_TIMER_INTCLR	0x14

#define HISI_TIMER_RIS		0x18

#define HISI_TIMER_MIS		0x1c

#define HISI_TIMER_BGLOAD	0x20

#define HISI_TIMER_BGLOAD_H	0x24





struct sp804_timer __initdata arm_sp804_timer = {

	.load		= TIMER_LOAD,

	.value		= TIMER_VALUE,

	.ctrl		= TIMER_CTRL,

	.intclr		= TIMER_INTCLR,

	.timer_base	= {TIMER_1_BASE, TIMER_2_BASE},

	.width		= 32,

};



struct sp804_timer __initdata hisi_sp804_timer = {

	.load		= HISI_TIMER_LOAD,

	.load_h		= HISI_TIMER_LOAD_H,

	.value		= HISI_TIMER_VALUE,

	.value_h	= HISI_TIMER_VALUE_H,

	.ctrl		= HISI_TIMER_CTRL,

	.intclr		= HISI_TIMER_INTCLR,

	.timer_base	= {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE},

	.width		= 64,

};



static struct sp804_clkevt sp804_clkevt[NR_TIMERS];



static long __init sp804_get_clock_rate(struct clk *clk, const char *name)

{

	long rate;

	int err;



	if (!clk)

		clk = clk_get_sys("sp804", name);

	if (IS_ERR(clk)) {

		pr_err("sp804: %s clock not found: %ld\n", name, PTR_ERR(clk));

		return PTR_ERR(clk);

	}



	err = clk_prepare(clk);

	if (err) {

		pr_err("sp804: clock failed to prepare: %d\n", err);
@@ -53,50 +95,57 @@ static long __init sp804_get_clock_rate(struct clk *clk) 
	return rate;

}



static void __iomem *sched_clock_base;



static u64 notrace sp804_read(void)

static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base)

{

	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);

	int i;



	for (i = 0; i < NR_TIMERS; i++) {

		if (sp804_clkevt[i].base == base)

			return &sp804_clkevt[i];

	}



	/* It's impossible to reach here */

	WARN_ON(1);



	return NULL;

}



void __init sp804_timer_disable(void __iomem *base)

static struct sp804_clkevt *sched_clkevt;



static u64 notrace sp804_read(void)

{

	writel(0, base + TIMER_CTRL);

	return ~readl_relaxed(sched_clkevt->value);

}



int  __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,

int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,

						  const char *name,

						  struct clk *clk,

						  int use_sched_clock)

{

	long rate;

	struct sp804_clkevt *clkevt;



	if (!clk) {

		clk = clk_get_sys("sp804", name);

		if (IS_ERR(clk)) {

			pr_err("sp804: clock not found: %d\n",

			       (int)PTR_ERR(clk));

			return PTR_ERR(clk);

		}

	}



	rate = sp804_get_clock_rate(clk);

	rate = sp804_get_clock_rate(clk, name);

	if (rate < 0)

		return -EINVAL;



	/* setup timer 0 as free-running clocksource */

	writel(0, base + TIMER_CTRL);

	writel(0xffffffff, base + TIMER_LOAD);

	writel(0xffffffff, base + TIMER_VALUE);

	clkevt = sp804_clkevt_get(base);



	writel(0, clkevt->ctrl);

	writel(0xffffffff, clkevt->load);

	writel(0xffffffff, clkevt->value);

	if (clkevt->width == 64) {

		writel(0xffffffff, clkevt->load_h);

		writel(0xffffffff, clkevt->value_h);

	}

	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,

		base + TIMER_CTRL);

		clkevt->ctrl);



	clocksource_mmio_init(base + TIMER_VALUE, name,

	clocksource_mmio_init(clkevt->value, name,

		rate, 200, 32, clocksource_mmio_readl_down);



	if (use_sched_clock) {

		sched_clock_base = base;

		sched_clkevt = clkevt;

		sched_clock_register(sp804_read, 32, rate);

	}
@@ -104,8 +153,7 @@ int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, 
}





static void __iomem *clkevt_base;

static unsigned long clkevt_reload;

static struct sp804_clkevt *common_clkevt;



/*

 * IRQ handler for the timer
@@ -115,7 +163,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) 
	struct clock_event_device *evt = dev_id;



	/* clear the interrupt */

	writel(1, clkevt_base + TIMER_INTCLR);

	writel(1, common_clkevt->intclr);



	evt->event_handler(evt);
@@ -124,7 +172,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) 


static inline void timer_shutdown(struct clock_event_device *evt)

{

	writel(0, clkevt_base + TIMER_CTRL);

	writel(0, common_clkevt->ctrl);

}



static int sp804_shutdown(struct clock_event_device *evt)
@@ -139,8 +187,8 @@ static int sp804_set_periodic(struct clock_event_device *evt) 
			     TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;



	timer_shutdown(evt);

	writel(clkevt_reload, clkevt_base + TIMER_LOAD);

	writel(ctrl, clkevt_base + TIMER_CTRL);

	writel(common_clkevt->reload, common_clkevt->load);

	writel(ctrl, common_clkevt->ctrl);

	return 0;

}
@@ -150,8 +198,8 @@ static int sp804_set_next_event(unsigned long next, 
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |

			     TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;



	writel(next, clkevt_base + TIMER_LOAD);

	writel(ctrl, clkevt_base + TIMER_CTRL);

	writel(next, common_clkevt->load);

	writel(ctrl, common_clkevt->ctrl);



	return 0;

}
@@ -168,30 +216,23 @@ static struct clock_event_device sp804_clockevent = { 
	.rating			= 300,

};



int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)

int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,

				  struct clk *clk, const char *name)

{

	struct clock_event_device *evt = &sp804_clockevent;

	long rate;



	if (!clk)

		clk = clk_get_sys("sp804", name);

	if (IS_ERR(clk)) {

		pr_err("sp804: %s clock not found: %d\n", name,

			(int)PTR_ERR(clk));

		return PTR_ERR(clk);

	}



	rate = sp804_get_clock_rate(clk);

	rate = sp804_get_clock_rate(clk, name);

	if (rate < 0)

		return -EINVAL;



	clkevt_base = base;

	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);

	common_clkevt = sp804_clkevt_get(base);

	common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ);

	evt->name = name;

	evt->irq = irq;

	evt->cpumask = cpu_possible_mask;



	writel(0, base + TIMER_CTRL);

	writel(0, common_clkevt->ctrl);



	if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,

			"timer", &sp804_clockevent))
@@ -201,10 +242,33 @@ int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct 
	return 0;

}



static int __init sp804_of_init(struct device_node *np)

static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base)

{

	int i;



	for (i = 0; i < NR_TIMERS; i++) {

		void __iomem *timer_base;

		struct sp804_clkevt *clkevt;



		timer_base = base + timer->timer_base[i];

		clkevt = &sp804_clkevt[i];

		clkevt->base	= timer_base;

		clkevt->load	= timer_base + timer->load;

		clkevt->load_h	= timer_base + timer->load_h;

		clkevt->value	= timer_base + timer->value;

		clkevt->value_h	= timer_base + timer->value_h;

		clkevt->ctrl	= timer_base + timer->ctrl;

		clkevt->intclr	= timer_base + timer->intclr;

		clkevt->width	= timer->width;

	}

}



static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer)

{

	static bool initialized = false;

	void __iomem *base;

	void __iomem *timer1_base;

	void __iomem *timer2_base;

	int irq, ret = -EINVAL;

	u32 irq_num = 0;

	struct clk *clk1, *clk2;
@@ -214,9 +278,12 @@ static int __init sp804_of_init(struct device_node *np) 
	if (!base)

		return -ENXIO;



	timer1_base = base + timer->timer_base[0];

	timer2_base = base + timer->timer_base[1];



	/* Ensure timers are disabled */

	writel(0, base + TIMER_CTRL);

	writel(0, base + TIMER_2_BASE + TIMER_CTRL);

	writel(0, timer1_base + timer->ctrl);

	writel(0, timer2_base + timer->ctrl);



	if (initialized || !of_device_is_available(np)) {

		ret = -EINVAL;
@@ -242,23 +309,26 @@ static int __init sp804_of_init(struct device_node *np) 
	if (irq <= 0)

		goto err;



	sp804_clkevt_init(timer, base);



	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);

	if (irq_num == 2) {



		ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);

		ret = sp804_clockevents_init(timer2_base, irq, clk2, name);

		if (ret)

			goto err;



		ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);

		ret = sp804_clocksource_and_sched_clock_init(timer1_base,

							     name, clk1, 1);

		if (ret)

			goto err;

	} else {



		ret = __sp804_clockevents_init(base, irq, clk1 , name);

		ret = sp804_clockevents_init(timer1_base, irq, clk1, name);

		if (ret)

			goto err;



		ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,

		ret = sp804_clocksource_and_sched_clock_init(timer2_base,

							     name, clk2, 1);

		if (ret)

			goto err;
@@ -270,7 +340,18 @@ static int __init sp804_of_init(struct device_node *np) 
	iounmap(base);

	return ret;

}

TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);



static int __init arm_sp804_of_init(struct device_node *np)

{

	return sp804_of_init(np, &arm_sp804_timer);

}

TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init);



static int __init hisi_sp804_of_init(struct device_node *np)

{

	return sp804_of_init(np, &hisi_sp804_timer);

}

TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init);



static int __init integrator_cp_of_init(struct device_node *np)

{
@@ -293,13 +374,16 @@ static int __init integrator_cp_of_init(struct device_node *np) 
	}



	/* Ensure timer is disabled */

	writel(0, base + TIMER_CTRL);

	writel(0, base + arm_sp804_timer.ctrl);



	if (init_count == 2 || !of_device_is_available(np))

		goto err;



	sp804_clkevt_init(&arm_sp804_timer, base);



	if (!init_count) {

		ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);

		ret = sp804_clocksource_and_sched_clock_init(base,

							     name, clk, 0);

		if (ret)

			goto err;

	} else {
@@ -307,7 +391,7 @@ static int __init integrator_cp_of_init(struct device_node *np) 
		if (irq <= 0)

			goto err;



		ret = __sp804_clockevents_init(base, irq, clk, name);

		ret = sp804_clockevents_init(base, irq, clk, name);

		if (ret)

			goto err;

	}

include/clocksource/timer-sp804.h

deleted100644 → 0
+0 −29
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __CLKSOURCE_TIMER_SP804_H

#define __CLKSOURCE_TIMER_SP804_H



struct clk;



int __sp804_clocksource_and_sched_clock_init(void __iomem *,

					     const char *, struct clk *, int);

int __sp804_clockevents_init(void __iomem *, unsigned int,

			     struct clk *, const char *);

void sp804_timer_disable(void __iomem *);



static inline void sp804_clocksource_init(void __iomem *base, const char *name)

{

	__sp804_clocksource_and_sched_clock_init(base, name, NULL, 0);

}



static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,

							  const char *name)

{

	__sp804_clocksource_and_sched_clock_init(base, name, NULL, 1);

}



static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name)

{

	__sp804_clockevents_init(base, irq, NULL, name);



}

#endif