Commit 3afbe13c authored by Mark's avatar Mark Committed by Greg Kroah-Hartman
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Staging: comedi: Coding style cleanups in adv_pci_dio.c 



This patch fixes up many coding style issues in adv_pci_dio.c found by
checkpatch.pl

Signed-off-by: default avatarMark Rankilor <reodge@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 5e95efec

drivers/staging/comedi/drivers/adv_pci_dio.c

+180 −127
Original line number Diff line number Diff line
@@ -67,9 +67,12 @@ enum hw_io_access { 


#define MAX_DI_SUBDEVS	2	/* max number of DI subdevices per card */

#define MAX_DO_SUBDEVS	2	/* max number of DO subdevices per card */

#define MAX_DIO_SUBDEVG	2	/* max number of DIO subdevices group per card */

#define MAX_8254_SUBDEVS   1	/* max number of 8254 counter subdevs per card */

				/* (could be more than one 8254 per subdevice) */

#define MAX_DIO_SUBDEVG	2	/* max number of DIO subdevices group per

				 * card */

#define MAX_8254_SUBDEVS   1	/* max number of 8254 counter subdevs per

				 * card */

				/* (could be more than one 8254 per

				 * subdevice) */



#define SIZE_8254	   4	/* 8254 IO space length */

#define SIZE_8255	   4	/* 8255 IO space length */
@@ -84,7 +87,8 @@ enum hw_io_access { 
#define PCI1730_DO	   2	/* W:   Digital output 0-15 */

#define PCI1733_IDI	   0	/* R:   Isolated digital input  0-31 */

#define	PCI1730_3_INT_EN	0x08	/* R/W: enable/disable interrupts */

#define	PCI1730_3_INT_RF	0x0c	/* R/W: set falling/raising edge for interrupts */

#define	PCI1730_3_INT_RF	0x0c	/* R/W: set falling/raising edge for

					 * interrupts */

#define	PCI1730_3_INT_CLR	0x10	/* R/W: clear interrupts */

#define PCI1734_IDO	   0	/* W:   Isolated digital output 0-31 */

#define PCI173x_BOARDID	   4	/* R:   Board I/D switch for 1730/3/4 */
@@ -99,7 +103,8 @@ enum hw_io_access { 
#define PCI1736_IDI        0	/* R:   Isolated digital input  0-15 */

#define PCI1736_IDO        0	/* W:   Isolated digital output 0-15 */

#define PCI1736_3_INT_EN        0x08	/* R/W: enable/disable interrupts */

#define PCI1736_3_INT_RF        0x0c	/* R/W: set falling/raising edge for interrupts */

#define PCI1736_3_INT_RF        0x0c	/* R/W: set falling/raising edge for

					 * interrupts */

#define PCI1736_3_INT_CLR       0x10	/* R/W: clear interrupts */

#define PCI1736_BOARDID    4	/* R:   Board I/D switch for 1736UP */

#define PCI1736_MAINREG    0	/* Normal register (2) doesn't work */
@@ -161,37 +166,66 @@ enum hw_io_access { 
#define INTCSR3		0x3b



/*  PCI-1760 mailbox commands */

#define CMD_ClearIMB2		0x00	/* Clear IMB2 status and return actaul DI status in IMB3 */

#define CMD_ClearIMB2		0x00	/* Clear IMB2 status and return actual

					 * DI status in IMB3 */

#define CMD_SetRelaysOutput	0x01	/* Set relay output from OMB0 */

#define CMD_GetRelaysStatus	0x02	/* Get relay status to IMB0 */

#define CMD_ReadCurrentStatus	0x07	/* Read the current status of the register in OMB0, result in IMB0 */

#define CMD_ReadFirmwareVersion	0x0e	/* Read the firmware ver., result in IMB1.IMB0 */

#define CMD_ReadHardwareVersion	0x0f	/* Read the hardware ver., result in IMB1.IMB0 */

#define CMD_EnableIDIFilters	0x20	/* Enable IDI filters based on bits in OMB0 */

#define CMD_EnableIDIPatternMatch 0x21	/* Enable IDI pattern match based on bits in OMB0 */

#define CMD_SetIDIPatternMatch	0x22	/* Enable IDI pattern match based on bits in OMB0 */

#define CMD_EnableIDICounters	0x28	/* Enable IDI counters based on bits in OMB0 */

#define CMD_ResetIDICounters	0x29	/* Reset IDI counters based on bits in OMB0 to its reset values */

#define CMD_OverflowIDICounters	0x2a	/* Enable IDI counters overflow interrupts  based on bits in OMB0 */

#define CMD_MatchIntIDICounters	0x2b	/* Enable IDI counters match value interrupts  based on bits in OMB0 */

#define CMD_EdgeIDICounters	0x2c	/* Set IDI up counters count edge (bit=0 - rising, =1 - falling) */

#define CMD_GetIDICntCurValue	0x2f	/* Read IDI{OMB0} up counter current value */

#define CMD_SetIDI0CntResetValue 0x40	/* Set IDI0 Counter Reset Value 256*OMB1+OMB0 */

#define CMD_SetIDI1CntResetValue 0x41	/* Set IDI1 Counter Reset Value 256*OMB1+OMB0 */

#define CMD_SetIDI2CntResetValue 0x42	/* Set IDI2 Counter Reset Value 256*OMB1+OMB0 */

#define CMD_SetIDI3CntResetValue 0x43	/* Set IDI3 Counter Reset Value 256*OMB1+OMB0 */

#define CMD_SetIDI4CntResetValue 0x44	/* Set IDI4 Counter Reset Value 256*OMB1+OMB0 */

#define CMD_SetIDI5CntResetValue 0x45	/* Set IDI5 Counter Reset Value 256*OMB1+OMB0 */

#define CMD_SetIDI6CntResetValue 0x46	/* Set IDI6 Counter Reset Value 256*OMB1+OMB0 */

#define CMD_SetIDI7CntResetValue 0x47	/* Set IDI7 Counter Reset Value 256*OMB1+OMB0 */

#define CMD_SetIDI0CntMatchValue 0x48	/* Set IDI0 Counter Match Value 256*OMB1+OMB0 */

#define CMD_SetIDI1CntMatchValue 0x49	/* Set IDI1 Counter Match Value 256*OMB1+OMB0 */

#define CMD_SetIDI2CntMatchValue 0x4a	/* Set IDI2 Counter Match Value 256*OMB1+OMB0 */

#define CMD_SetIDI3CntMatchValue 0x4b	/* Set IDI3 Counter Match Value 256*OMB1+OMB0 */

#define CMD_SetIDI4CntMatchValue 0x4c	/* Set IDI4 Counter Match Value 256*OMB1+OMB0 */

#define CMD_SetIDI5CntMatchValue 0x4d	/* Set IDI5 Counter Match Value 256*OMB1+OMB0 */

#define CMD_SetIDI6CntMatchValue 0x4e	/* Set IDI6 Counter Match Value 256*OMB1+OMB0 */

#define CMD_SetIDI7CntMatchValue 0x4f	/* Set IDI7 Counter Match Value 256*OMB1+OMB0 */

#define CMD_ReadCurrentStatus	0x07	/* Read the current status of the

					 * register in OMB0, result in IMB0 */

#define CMD_ReadFirmwareVersion	0x0e	/* Read the firmware ver., result in

					 * IMB1.IMB0 */

#define CMD_ReadHardwareVersion	0x0f	/* Read the hardware ver., result in

					 * IMB1.IMB0 */

#define CMD_EnableIDIFilters	0x20	/* Enable IDI filters based on bits in

					 * OMB0 */

#define CMD_EnableIDIPatternMatch 0x21	/* Enable IDI pattern match based on

					 * bits in OMB0 */

#define CMD_SetIDIPatternMatch	0x22	/* Enable IDI pattern match based on

					 * bits in OMB0 */

#define CMD_EnableIDICounters	0x28	/* Enable IDI counters based on bits in

					 * OMB0 */

#define CMD_ResetIDICounters	0x29	/* Reset IDI counters based on bits in

					 * OMB0 to its reset values */

#define CMD_OverflowIDICounters	0x2a	/* Enable IDI counters overflow

					 * interrupts  based on bits in OMB0 */

#define CMD_MatchIntIDICounters	0x2b	/* Enable IDI counters match value

					 * interrupts  based on bits in OMB0 */

#define CMD_EdgeIDICounters	0x2c	/* Set IDI up counters count edge (bit=0

					 * - rising, =1 - falling) */

#define CMD_GetIDICntCurValue	0x2f	/* Read IDI{OMB0} up counter current

					 * value */

#define CMD_SetIDI0CntResetValue 0x40	/* Set IDI0 Counter Reset Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI1CntResetValue 0x41	/* Set IDI1 Counter Reset Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI2CntResetValue 0x42	/* Set IDI2 Counter Reset Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI3CntResetValue 0x43	/* Set IDI3 Counter Reset Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI4CntResetValue 0x44	/* Set IDI4 Counter Reset Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI5CntResetValue 0x45	/* Set IDI5 Counter Reset Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI6CntResetValue 0x46	/* Set IDI6 Counter Reset Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI7CntResetValue 0x47	/* Set IDI7 Counter Reset Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI0CntMatchValue 0x48	/* Set IDI0 Counter Match Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI1CntMatchValue 0x49	/* Set IDI1 Counter Match Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI2CntMatchValue 0x4a	/* Set IDI2 Counter Match Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI3CntMatchValue 0x4b	/* Set IDI3 Counter Match Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI4CntMatchValue 0x4c	/* Set IDI4 Counter Match Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI5CntMatchValue 0x4d	/* Set IDI5 Counter Match Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI6CntMatchValue 0x4e	/* Set IDI6 Counter Match Value

					 * 256*OMB1+OMB0 */

#define CMD_SetIDI7CntMatchValue 0x4f	/* Set IDI7 Counter Match Value

					 * 256*OMB1+OMB0 */



#define OMBCMD_RETRY	0x03	/* 3 times try request before error */
@@ -373,9 +407,12 @@ struct pci_dio_private { 
	char GlobalIrqEnabled;	/*  1= any IRQ source is enabled */

	/*  PCI-1760 specific data */

	unsigned char IDICntEnable;	/* counter's counting enable status */

	unsigned char IDICntOverEnable;	/*  counter's overflow interrupts enable status */

	unsigned char IDICntMatchEnable;	/*  counter's match interrupts enable status */

	unsigned char IDICntEdge;	/*  counter's count edge value (bit=0 - rising, =1 - falling) */

	unsigned char IDICntOverEnable;	/* counter's overflow interrupts enable

					 * status */

	unsigned char IDICntMatchEnable;	/* counter's match interrupts

						 * enable status */

	unsigned char IDICntEdge;	/* counter's count edge value

					 * (bit=0 - rising, =1 - falling) */

	unsigned short CntResValue[8];	/*  counters' reset value */

	unsigned short CntMatchValue[8]; /*  counters' match interrupt value */

	unsigned char IDIFiltersEn; /*  IDI's digital filters enable status */
@@ -691,7 +728,8 @@ static int pci1760_insn_cnt_write(struct comedi_device *dev, 
	};

	unsigned char imb[4];



	if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {	/*  Set reset value if different */

	/* Set reset value if different */

	if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {

		ret = pci1760_mbxrequest(dev, omb, imb);

		if (!ret)

			return ret;
@@ -704,7 +742,8 @@ static int pci1760_insn_cnt_write(struct comedi_device *dev, 
	if (!ret)

		return ret;



	if (!(bitmask & devpriv->IDICntEnable)) {	/*  start counter if it don't run */

	/*  start counter if it don't run */

	if (!(bitmask & devpriv->IDICntEnable)) {

		omb[0] = bitmask;

		omb[2] = CMD_EnableIDICounters;

		ret = pci1760_mbxrequest(dev, omb, imb);
@@ -740,12 +779,14 @@ static int pci1760_reset(struct comedi_device *dev) 
	devpriv->IDICntEnable = 0;



	omb[0] = 0x00;

	omb[2] = CMD_OverflowIDICounters;	/*  disable counters overflow interrupts */

	omb[2] = CMD_OverflowIDICounters; /* disable counters overflow

					   * interrupts */

	pci1760_mbxrequest(dev, omb, imb);

	devpriv->IDICntOverEnable = 0;



	omb[0] = 0x00;

	omb[2] = CMD_MatchIntIDICounters;	/*  disable counters match value interrupts */

	omb[2] = CMD_MatchIntIDICounters; /* disable counters match value

					   * interrupts */

	pci1760_mbxrequest(dev, omb, imb);

	devpriv->IDICntMatchEnable = 0;
@@ -766,7 +807,8 @@ static int pci1760_reset(struct comedi_device *dev) 
	}



	omb[0] = 0xff;

	omb[2] = CMD_ResetIDICounters;	/*  reset IDI up counters to reset values */

	omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset

					* values */

	pci1760_mbxrequest(dev, omb, imb);



	omb[0] = 0x00;
@@ -807,9 +849,12 @@ static int pci_dio_reset(struct comedi_device *dev) 
		outb(0, dev->iobase + PCI1730_IDO + 1);

		/* NO break there! */

	case TYPE_PCI1733:

		outb(0, dev->iobase + PCI1730_3_INT_EN);	/*  disable interrupts */

		outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);	/*  clear interrupts */

		outb(0, dev->iobase + PCI1730_3_INT_RF);	/*  set rising edge trigger */

		/* disable interrupts */

		outb(0, dev->iobase + PCI1730_3_INT_EN);

		/* clear interrupts */

		outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);

		/* set rising edge trigger */

		outb(0, dev->iobase + PCI1730_3_INT_RF);

		break;

	case TYPE_PCI1734:

		outb(0, dev->iobase + PCI1734_IDO);	/*  clear outputs */
@@ -830,43 +875,53 @@ static int pci_dio_reset(struct comedi_device *dev) 
	case TYPE_PCI1736:

		outb(0, dev->iobase + PCI1736_IDO);

		outb(0, dev->iobase + PCI1736_IDO + 1);

		outb(0, dev->iobase + PCI1736_3_INT_EN);	/*  disable interrupts */

		outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);	/*  clear interrupts */

		outb(0, dev->iobase + PCI1736_3_INT_RF);	/*  set rising edge trigger */

		/* disable interrupts */

		outb(0, dev->iobase + PCI1736_3_INT_EN);

		/* clear interrupts */

		outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);

		/* set rising edge trigger */

		outb(0, dev->iobase + PCI1736_3_INT_RF);

		break;



	case TYPE_PCI1750:

	case TYPE_PCI1751:

		outb(0x88, dev->iobase + PCI1750_ICR);	/*  disable & clear interrupts */

		/* disable & clear interrupts */

		outb(0x88, dev->iobase + PCI1750_ICR);

		break;

	case TYPE_PCI1752:

		outw(0, dev->iobase + PCI1752_6_CFC);	/*  disable channel freeze function */

		outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze

						       * function */

		outw(0, dev->iobase + PCI1752_IDO);	/*  clear outputs */

		outw(0, dev->iobase + PCI1752_IDO + 2);

		outw(0, dev->iobase + PCI1752_IDO2);

		outw(0, dev->iobase + PCI1752_IDO2 + 2);

		break;

	case TYPE_PCI1753E:

		outb(0x88, dev->iobase + PCI1753E_ICR0);	/*  disable & clear interrupts */

		outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear

							  * interrupts */

		outb(0x80, dev->iobase + PCI1753E_ICR1);

		outb(0x80, dev->iobase + PCI1753E_ICR2);

		outb(0x80, dev->iobase + PCI1753E_ICR3);

		/* NO break there! */

	case TYPE_PCI1753:

		outb(0x88, dev->iobase + PCI1753_ICR0);	/*  disable & clear interrupts */

		outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear

							 * interrupts */

		outb(0x80, dev->iobase + PCI1753_ICR1);

		outb(0x80, dev->iobase + PCI1753_ICR2);

		outb(0x80, dev->iobase + PCI1753_ICR3);

		break;

	case TYPE_PCI1754:

		outw(0x08, dev->iobase + PCI1754_6_ICR0);	/*  disable and clear interrupts */

		outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear

							   * interrupts */

		outw(0x08, dev->iobase + PCI1754_6_ICR1);

		outw(0x08, dev->iobase + PCI1754_ICR2);

		outw(0x08, dev->iobase + PCI1754_ICR3);

		break;

	case TYPE_PCI1756:

		outw(0, dev->iobase + PCI1752_6_CFC);	/*  disable channel freeze function */

		outw(0x08, dev->iobase + PCI1754_6_ICR0);	/*  disable and clear interrupts */

		outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze

						       * function */

		outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear

							   * interrupts */

		outw(0x08, dev->iobase + PCI1754_6_ICR1);

		outw(0, dev->iobase + PCI1756_IDO);	/*  clear outputs */

		outw(0, dev->iobase + PCI1756_IDO + 2);
@@ -875,7 +930,8 @@ static int pci_dio_reset(struct comedi_device *dev) 
		pci1760_reset(dev);

		break;

	case TYPE_PCI1762:

		outw(0x0101, dev->iobase + PCI1762_ICR);	/*  disable & clear interrupts */

		outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear

							  * interrupts */

		break;

	}
@@ -1215,15 +1271,12 @@ static int pci_dio_detach(struct comedi_device *dev) 
			}

		}



		if (this_board->boardid.chans) {

		if (this_board->boardid.chans)

			subdev++;

		}



		for (i = 0; i < MAX_8254_SUBDEVS; i++) {

			if (this_board->s8254[i].chans) {

		for (i = 0; i < MAX_8254_SUBDEVS; i++)

			if (this_board->s8254[i].chans)

				subdev++;

			}

		}



		for (i = 0; i < dev->n_subdevices; i++) {

			s = dev->subdevices + i;