Commit 36154b68 authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab
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media: ccs-pll: Fix VT post-PLL divisor calculation 



The PLL calculator only searched even total divisor values apart from one,
but this is wrong: the total divisor is odd in cases where system divisor
is one. Fix this by including odd total PLL values where system divisor is
one to the search.

Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 594f1e93

drivers/media/i2c/ccs-pll.c

+7 −5
Original line number Diff line number Diff line
@@ -347,14 +347,16 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, 
	 * into a value which is not smaller than div, the desired

	 * divisor.

	 */

	for (vt_div = min_vt_div; vt_div <= max_vt_div;

	     vt_div += 2 - (vt_div & 1)) {

		for (sys_div = min_sys_div;

		     sys_div <= max_sys_div;

	for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) {

		uint16_t __max_sys_div = vt_div & 1 ? 1 : max_sys_div;



		for (sys_div = min_sys_div; sys_div <= __max_sys_div;

		     sys_div += 2 - (sys_div & 1)) {

			uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);

			uint16_t pix_div;

			uint16_t rounded_div;



			pix_div = DIV_ROUND_UP(vt_div, sys_div);



			if (pix_div < lim->vt_bk.min_pix_clk_div

			    || pix_div > lim->vt_bk.max_pix_clk_div) {

				dev_dbg(dev,