Commit 594f1e93 authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab
Browse files

media: ccs-pll: Make VT divisors 16-bit 



Make VT divisors 16-bit unsigned numbers. They don't need 32 bits after
all.

Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent f25d3962

drivers/media/i2c/ccs-pll.c

+25 −26
Original line number Diff line number Diff line
@@ -239,11 +239,11 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, 
		     struct ccs_pll_branch_bk *op_pll_bk, bool cphy,

		     uint32_t phy_const)

{

	uint32_t sys_div;

	uint32_t best_pix_div = INT_MAX >> 1;

	uint32_t vt_op_binning_div;

	uint32_t min_vt_div, max_vt_div, vt_div;

	uint32_t min_sys_div, max_sys_div;

	uint16_t sys_div;

	uint16_t best_pix_div = SHRT_MAX >> 1;

	uint16_t vt_op_binning_div;

	uint16_t min_vt_div, max_vt_div, vt_div;

	uint16_t min_sys_div, max_sys_div;



	if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)

		goto out_calc_pixel_rate;
@@ -297,19 +297,18 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, 


	/* Find smallest and biggest allowed vt divisor. */

	dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);

	min_vt_div = max(min_vt_div,

	min_vt_div = max_t(uint16_t, min_vt_div,

			   DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,

					lim->vt_bk.max_pix_clk_freq_hz));

	dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",

		min_vt_div);

	min_vt_div = max_t(uint32_t, min_vt_div,

			   lim->vt_bk.min_pix_clk_div

	min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div

						 * lim->vt_bk.min_sys_clk_div);

	dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);



	max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;

	dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);

	max_vt_div = min(max_vt_div,

	max_vt_div = min_t(uint16_t, max_vt_div,

			   DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,

				      lim->vt_bk.min_pix_clk_freq_hz));

	dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
@@ -321,11 +320,11 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, 
	 */

	min_sys_div = lim->vt_bk.min_sys_clk_div;

	dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);

	min_sys_div = max(min_sys_div,

	min_sys_div = max_t(uint16_t, min_sys_div,

			    DIV_ROUND_UP(min_vt_div,

					 lim->vt_bk.max_pix_clk_div));

	dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);

	min_sys_div = max(min_sys_div,

	min_sys_div = max_t(uint16_t, min_sys_div,

			    pll_fr->pll_op_clk_freq_hz

			    / lim->vt_bk.max_sys_clk_freq_hz);

	dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
@@ -334,11 +333,11 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, 


	max_sys_div = lim->vt_bk.max_sys_clk_div;

	dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);

	max_sys_div = min(max_sys_div,

	max_sys_div = min_t(uint16_t, max_sys_div,

			    DIV_ROUND_UP(max_vt_div,

					 lim->vt_bk.min_pix_clk_div));

	dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);

	max_sys_div = min(max_sys_div,

	max_sys_div = min_t(uint16_t, max_sys_div,

			    DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,

					 lim->vt_bk.min_pix_clk_freq_hz));

	dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
@@ -376,7 +375,7 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, 
			if (vt_div == rounded_div)

				break;

		}

		if (best_pix_div < INT_MAX >> 1)

		if (best_pix_div < SHRT_MAX >> 1)

			break;

	}