Commit 2df8aa03 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'hisi-arm64-dt-for-5.11' of git://github.com/hisilicon/linux-hisi into arm/dt 

ARM64: DT: Hisilicon ARM64 DT updates for 5.11

- Cleanups of the hisilicon DTS to align with the dtschema. All of them do not
  have any functional effect except passing dtschema checks or dtc W=2 builds.

* tag 'hisi-arm64-dt-for-5.11' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios"
  arm64: dts: hi3660: Harmonize DWC USB3 DT nodes name
  arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml
  arm64: dts: hisilicon: list all clocks required by pl011.yaml
  arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml
  arm64: dts: hisilicon: normalize the node name of the UART devices
  arm64: dts: hisilicon: normalize the node name of the usb devices
  arm64: dts: hisilicon: normalize the node name of the SMMU devices
  arm64: dts: hisilicon: place clock-names "biu" before "ciu"
  arm64: dts: hisilicon: remove unused property pinctrl-names
  arm64: dts: hisilicon: write the values of property-units into a uint32 array
  arm64: dts: hisilicon: separate each group of data in the property "reg"
  arm64: dts: hisilicon: normalize the node name of the ITS devices

Link: https://lore.kernel.org/r/5FBDC416.5060008@hisilicon.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 3319f148 25df3e1f

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

+7 −6
Original line number Diff line number Diff line
@@ -971,8 +971,8 @@ spi2: spi@ffd68000 { 
			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;

			clock-names = "apb_pclk";

			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>;

			clock-names = "sspclk", "apb_pclk";

			pinctrl-names = "default";

			pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;

			num-cs = <1>;
@@ -986,8 +986,8 @@ spi3: spi@ff3b3000 { 
			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;

			clock-names = "apb_pclk";

			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>;

			clock-names = "sspclk", "apb_pclk";

			pinctrl-names = "default";

			pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;

			num-cs = <1>;
@@ -1045,7 +1045,8 @@ ufs: ufs@ff3b0000 { 
			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,

				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;

			clock-names = "ref_clk", "phy_clk";

			freq-table-hz = <0 0>, <0 0>;

			freq-table-hz = <0 0

					 0 0>;

			/* offset: 0x84; bit: 12 */

			resets = <&crg_rst 0x84 12>;

			reset-names = "rst";
@@ -1168,7 +1169,7 @@ usb_phy: usb-phy { 
			};

		};



		dwc3: dwc3@ff100000 {

		dwc3: usb@ff100000 {

			compatible = "snps,dwc3";

			reg = <0x0 0xff100000 0x0 0x100000>;

arch/arm64/boot/dts/hisilicon/hi3670.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -213,7 +213,6 @@ uart1: serial@fdf00000 { 
			clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,

				 <&crg_ctrl HI3670_PCLK>;

			clock-names = "uartclk", "apb_pclk";

			pinctrl-names = "default";

			status = "disabled";

		};
@@ -260,7 +259,6 @@ uart5: serial@fdf05000 { 
			clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,

				 <&crg_ctrl HI3670_PCLK>;

			clock-names = "uartclk", "apb_pclk";

			pinctrl-names = "default";

			status = "disabled";

		};
@@ -667,7 +665,8 @@ ufs: ufs@ff3c0000 { 
			clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,

				<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;

			clock-names = "ref_clk", "phy_clk";

			freq-table-hz = <0 0>, <0 0>;

			freq-table-hz = <0 0

					 0 0>;

			/* offset: 0x84; bit: 12 */

			resets = <&crg_rst 0x84 12>;

			reset-names = "rst";

arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi

+13 −14
Original line number Diff line number Diff line
@@ -91,11 +91,10 @@ crg: clock-reset-controller@8a22000 { 
			gmacphyrst: reset-controller {

				compatible = "ti,syscon-reset";

				#reset-cells = <1>;

				ti,reset-bits =

					<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |

					 DEASSERT_SET|STATUS_NONE)>,

					<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |

					 DEASSERT_SET|STATUS_NONE)>;

				ti,reset-bits = <

					0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)

					0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)

				>;

			};

		};
@@ -217,8 +216,8 @@ uart0: serial@8b00000 { 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x8b00000 0x1000>;

			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sysctrl HISTB_UART0_CLK>;

			clock-names = "apb_pclk";

			clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};
@@ -226,8 +225,8 @@ uart2: serial@8b02000 { 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x8b02000 0x1000>;

			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HISTB_UART2_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};
@@ -292,8 +291,8 @@ spi0: spi@8b1a000 { 
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

			num-cs = <1>;

			cs-gpios = <&gpio7 1 0>;

			clocks = <&crg HISTB_SPI0_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>;

			clock-names = "sspclk", "apb_pclk";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";
@@ -305,7 +304,7 @@ sd0: mmc@9820000 { 
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HISTB_SDIO0_CIU_CLK>,

				 <&crg HISTB_SDIO0_BIU_CLK>;

			clock-names = "ciu", "biu";

			clock-names = "biu", "ciu";

			resets = <&crg 0x9c 4>;

			reset-names = "reset";

			status = "disabled";
@@ -585,7 +584,7 @@ pcie: pcie@9860000 { 
			status = "disabled";

		};



		ohci: ohci@9880000 {

		ohci: usb@9880000 {

			compatible = "generic-ohci";

			reg = <0x9880000 0x10000>;

			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
@@ -600,7 +599,7 @@ ohci: ohci@9880000 { 
			status = "disabled";

		};



		ehci: ehci@9890000 {

		ehci: usb@9890000 {

			compatible = "generic-ehci";

			reg = <0x9890000 0x10000>;

			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/hisilicon/hi6220.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -725,8 +725,8 @@ spi0: spi@f7106000 { 
			interrupts = <0 50 4>;

			bus-id = <0>;

			enable-dma = <0>;

			clocks = <&sys_ctrl HI6220_SPI_CLK>;

			clock-names = "apb_pclk";

			clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;

			clock-names = "sspclk", "apb_pclk";

			pinctrl-names = "default";

			pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;

			num-cs = <1>;

arch/arm64/boot/dts/hisilicon/hip05.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -242,28 +242,28 @@ gic: interrupt-controller@8d000000 { 
		      <0x0 0xfe020000 0 0x10000>;       /* GICV */

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;



		its_peri: interrupt-controller@8c000000 {

		its_peri: msi-controller@8c000000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			#msi-cells = <1>;

			reg = <0x0 0x8c000000 0x0 0x40000>;

		};



		its_m3: interrupt-controller@a3000000 {

		its_m3: msi-controller@a3000000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			#msi-cells = <1>;

			reg = <0x0 0xa3000000 0x0 0x40000>;

		};



		its_pcie: interrupt-controller@b7000000 {

		its_pcie: msi-controller@b7000000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			#msi-cells = <1>;

			reg = <0x0 0xb7000000 0x0 0x40000>;

		};



		its_dsa: interrupt-controller@c6000000 {

		its_dsa: msi-controller@c6000000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			#msi-cells = <1>;
@@ -296,23 +296,23 @@ refclk200mhz: refclk200mhz { 
			clock-frequency = <200000000>;

		};



		uart0: uart@80300000 {

		uart0: serial@80300000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x0 0x80300000 0x0 0x10000>;

			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&refclk200mhz>;

			clock-names = "apb_pclk";

			clocks = <&refclk200mhz>, <&refclk200mhz>;

			clock-names = "baudclk", "apb_pclk";

			reg-shift = <2>;

			reg-io-width = <4>;

			status = "disabled";

		};



		uart1: uart@80310000 {

		uart1: serial@80310000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x0 0x80310000 0x0 0x10000>;

			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&refclk200mhz>;

			clock-names = "apb_pclk";

			clocks = <&refclk200mhz>, <&refclk200mhz>;

			clock-names = "baudclk", "apb_pclk";

			reg-shift = <2>;

			reg-io-width = <4>;

			status = "disabled";
@@ -335,7 +335,7 @@ porta: gpio-controller@0 { 
				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				ngpios = <32>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;
@@ -354,7 +354,7 @@ portb: gpio-controller@0 { 
				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				ngpios = <32>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;