Commit 2b5bbef5 authored by Oded Gabbay's avatar Oded Gabbay
Browse files

habanalabs: add asic property of host dma offset 



Each ASIC can have a different offset to add to a host dma address,
to enable the ASIC to access that host memory.

The usage for this can be common code so add this to the asic
property structure.

Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent d18bf13e

drivers/misc/habanalabs/common/habanalabs.h

+3 −0
Original line number Diff line number Diff line
@@ -434,6 +434,8 @@ struct hl_hints_range { 
 *                  the device's MMU.

 * @dram_hints_align_mask: dram va hint addresses alignment mask which is used

 *                  for hints validity check.

 * device_dma_offset_for_host_access: the offset to add to host DMA addresses

 *                                    to enable the device to access them.

 * @mmu_pgt_size: MMU page tables total size.

 * @mmu_pte_size: PTE size in MMU page tables.

 * @mmu_hop_table_size: MMU hop table size.
@@ -527,6 +529,7 @@ struct asic_fixed_properties { 
	u64				cb_va_start_addr;

	u64				cb_va_end_addr;

	u64				dram_hints_align_mask;

	u64				device_dma_offset_for_host_access;

	u32				mmu_pgt_size;

	u32				mmu_pte_size;

	u32				mmu_hop_table_size;

drivers/misc/habanalabs/gaudi/gaudi.c

+1 −0
Original line number Diff line number Diff line
@@ -537,6 +537,7 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev) 
						get_collective_mode(hdev, i);

	}



	prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;

	prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;

	prop->collective_first_sob = 0;

	prop->collective_first_mon = 0;

drivers/misc/habanalabs/goya/goya.c

+1 −0
Original line number Diff line number Diff line
@@ -389,6 +389,7 @@ int goya_set_fixed_properties(struct hl_device *hdev) 
		prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;

	}



	prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;

	prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;



	prop->dram_base_address = DRAM_PHYS_BASE;