Commit 26a0e208 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Drop unused link FPGA code 



There are multiple parts of the code that DC does not use anymore, and
this commit drops those dead codes.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6d1d1c7d

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

+0 −9
Original line number Diff line number Diff line
@@ -1723,15 +1723,6 @@ static void bios_parser_set_scratch_critical_state( 
	bios_set_scratch_critical_state(dcb, state);

}



struct atom_dig_transmitter_info_header_v5_3 {

    struct atom_common_table_header table_header;

    uint16_t dpphy_hdmi_settings_offset;

    uint16_t dpphy_dvi_settings_offset;

    uint16_t dpphy_dp_setting_table_offset;

    uint16_t uniphy_xbar_settings_v2_table_offset;

    uint16_t dpphy_internal_reg_overide_offset;

};



static enum bp_result bios_parser_get_firmware_info(

	struct dc_bios *dcb,

	struct dc_firmware_info *info)

drivers/gpu/drm/amd/display/dc/link/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_LINK) 
###############################################################################

# accessories

###############################################################################

LINK_ACCESSORIES = link_dp_trace.o link_dp_cts.o link_fpga.o

LINK_ACCESSORIES = link_dp_trace.o link_dp_cts.o



AMD_DAL_LINK_ACCESSORIES = $(addprefix $(AMDDALPATH)/dc/link/accessories/, \

$(LINK_ACCESSORIES))

drivers/gpu/drm/amd/display/dc/link/accessories/link_fpga.c

deleted100644 → 0
+0 −95
Original line number Diff line number Diff line 
/*

 * Copyright 2023 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */

#include "link_fpga.h"

#include "link/link_dpms.h"

#include "dm_helpers.h"

#include "link_hwss.h"

#include "dccg.h"

#include "resource.h"



#define DC_LOGGER_INIT(logger)



void dp_fpga_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)

{

	struct dc *dc = pipe_ctx->stream->ctx->dc;

	struct dc_stream_state *stream = pipe_ctx->stream;

	struct link_mst_stream_allocation_table proposed_table = {0};

	struct fixed31_32 avg_time_slots_per_mtp;

	uint8_t req_slot_count = 0;

	uint8_t vc_id = 1; /// VC ID always 1 for SST

	struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings;

	const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);

	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);



	stream->link->cur_link_settings = link_settings;



	if (link_hwss->ext.enable_dp_link_output)

		link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,

				stream->signal, pipe_ctx->clock_source->id,

				&link_settings);



	/* Enable DP_STREAM_ENC */

	dc->hwss.enable_stream(pipe_ctx);



	/* Set DPS PPS SDP (AKA "info frames") */

	if (pipe_ctx->stream->timing.flags.DSC) {

		link_set_dsc_pps_packet(pipe_ctx, true, true);

	}



	/* Allocate Payload */

	if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {

		// MST case

		uint8_t i;



		proposed_table.stream_count = state->stream_count;

		for (i = 0; i < state->stream_count; i++) {

			avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);

			req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);

			proposed_table.stream_allocations[i].slot_count = req_slot_count;

			proposed_table.stream_allocations[i].vcp_id = i+1;

			/* NOTE: This makes assumption that pipe_ctx index is same as stream index */

			proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;

		}

	} else {

		// SST case

		avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, stream->link);

		req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);

		proposed_table.stream_count = 1; /// Always 1 stream for SST

		proposed_table.stream_allocations[0].slot_count = req_slot_count;

		proposed_table.stream_allocations[0].vcp_id = vc_id;

		proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

	}



	link_hwss->ext.update_stream_allocation_table(stream->link,

			&pipe_ctx->link_res,

			&proposed_table);



	if (link_hwss->ext.set_throttled_vcp_size)

		link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);



	dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);

	dc->hwss.enable_audio_stream(pipe_ctx);

}

drivers/gpu/drm/amd/display/dc/link/accessories/link_fpga.h

deleted100644 → 0
+0 −30
Original line number Diff line number Diff line 
/*

 * Copyright 2023 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */

#ifndef __LINK_FPGA_H__

#define __LINK_FPGA_H__

#include "link.h"

void dp_fpga_hpo_enable_link_and_stream(struct dc_state *state,

		struct pipe_ctx *pipe_ctx);

#endif /* __LINK_FPGA_H__ */

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

+0 −1
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ 
#include "link_dpms.h"

#include "link_hwss.h"

#include "link_validation.h"

#include "accessories/link_fpga.h"

#include "accessories/link_dp_trace.h"

#include "protocols/link_dpcd.h"

#include "protocols/link_ddc.h"