ARMv7: Document the PRRR and NMRR registers setting

This patch adds a comment to the proc-v7.S file for the setting of the
PRRR and NMRR registers. It also sets the PRRR[13:12] bits to 0
(corresponding to the reserved TEX[0]CB encoding 110) to be consistent
with the documentation.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>