Commit 1f3cd090 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

wifi: rtw89: Add EHT rate mask as parameters of RA H2C command 



Set EHT rate mask to RA (rate adaptive) H2C command according to handshake
result. The EHT rate mask format looks like

  44               28               12        4    0
   +----------------+----------------+--------+----+
   |  EHT 2SS rate  |  EHT 1SS rate  |  OFDM  | CCK|
   +----------------+----------------+--------+----+

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231011115256.6121-4-pkshih@realtek.com
parent 786a93c9

drivers/net/wireless/realtek/rtw89/core.h

+1 −0
Original line number Diff line number Diff line
@@ -2734,6 +2734,7 @@ enum rtw89_ra_mode { 
	RTW89_RA_MODE_HT = BIT(2),

	RTW89_RA_MODE_VHT = BIT(3),

	RTW89_RA_MODE_HE = BIT(4),

	RTW89_RA_MODE_EHT = BIT(5),

};



enum rtw89_ra_report_mode {

drivers/net/wireless/realtek/rtw89/phy.c

+57 −1
Original line number Diff line number Diff line
@@ -88,6 +88,55 @@ static u64 get_he_ra_mask(struct ieee80211_sta *sta) 
	return get_mcs_ra_mask(mcs_map, 11, 2);

}



static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss)

{

	u64 nss_mcs_shift;

	u64 nss_mcs_val;

	u64 mask = 0;

	int i, j;

	u8 nss;



	for (i = 0; i < n_nss; i++) {

		nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX);

		if (!nss)

			continue;



		nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0);



		for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16)

			mask |= nss_mcs_val << nss_mcs_shift;

	}



	return mask;

}



static u64 get_eht_ra_mask(struct ieee80211_sta *sta)

{

	struct ieee80211_sta_eht_cap *eht_cap = &sta->deflink.eht_cap;

	struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz;

	struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss;



	switch (sta->deflink.bandwidth) {

	case IEEE80211_STA_RX_BW_320:

		mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;

		/* MCS 9, 11, 13 */

		return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);

	case IEEE80211_STA_RX_BW_160:

		mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;

		/* MCS 9, 11, 13 */

		return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);

	case IEEE80211_STA_RX_BW_80:

	default:

		mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;

		/* MCS 9, 11, 13 */

		return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);

	case IEEE80211_STA_RX_BW_20:

		mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz;

		/* MCS 7, 9, 11, 13 */

		return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4);

	}

}



#define RA_FLOOR_TABLE_SIZE	7

#define RA_FLOOR_UP_GAP		3

static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
@@ -194,6 +243,9 @@ rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 
static const u64

rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,

			     RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};

static const u64

rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES,

			      RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES};



static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev,

				struct rtw89_sta *rtwsta,
@@ -255,7 +307,11 @@ static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 


	memset(ra, 0, sizeof(*ra));

	/* Set the ra mask from sta's capability */

	if (sta->deflink.he_cap.has_he) {

	if (sta->deflink.eht_cap.has_eht) {

		mode |= RTW89_RA_MODE_EHT;

		ra_mask |= get_eht_ra_mask(sta);

		high_rate_masks = rtw89_ra_mask_eht_rates;

	} else if (sta->deflink.he_cap.has_he) {

		mode |= RTW89_RA_MODE_HE;

		csi_mode = RTW89_RA_RPT_MODE_HE;

		ra_mask |= get_he_ra_mask(sta);

drivers/net/wireless/realtek/rtw89/phy.h

+5 −0
Original line number Diff line number Diff line
@@ -46,6 +46,11 @@ 
#define RA_MASK_HE_3SS_RATES	GENMASK_ULL(47, 36)

#define RA_MASK_HE_4SS_RATES	GENMASK_ULL(59, 48)

#define RA_MASK_HE_RATES	GENMASK_ULL(59, 12)

#define RA_MASK_EHT_1SS_RATES	GENMASK_ULL(27, 12)

#define RA_MASK_EHT_2SS_RATES	GENMASK_ULL(43, 28)

#define RA_MASK_EHT_3SS_RATES	GENMASK_ULL(59, 44)

#define RA_MASK_EHT_4SS_RATES	GENMASK_ULL(62, 60)

#define RA_MASK_EHT_RATES	GENMASK_ULL(62, 12)



#define CFO_TRK_ENABLE_TH (2 << 2)

#define CFO_TRK_STOP_TH_4 (30 << 2)