Commit 1bae0cfe authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Borislav Petkov (AMD)
Browse files

x86/mce: Cleanup mce_usable_address() 



Move Intel-specific checks into a helper function.

Explicitly use "bool" for return type.

No functional change intended.

Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230613141142.36801-4-yazen.ghannam@amd.com
parent 48da1ad8

arch/x86/include/asm/mce.h

+1 −1
Original line number Diff line number Diff line
@@ -245,7 +245,7 @@ static inline void cmci_recheck(void) {} 
int mce_available(struct cpuinfo_x86 *c);

bool mce_is_memory_error(struct mce *m);

bool mce_is_correctable(struct mce *m);

int mce_usable_address(struct mce *m);

bool mce_usable_address(struct mce *m);



DECLARE_PER_CPU(unsigned, mce_exception_count);

DECLARE_PER_CPU(unsigned, mce_poll_count);

arch/x86/kernel/cpu/mce/core.c

+10 −23
Original line number Diff line number Diff line
@@ -453,35 +453,22 @@ static void mce_irq_work_cb(struct irq_work *entry) 
	mce_schedule_work();

}



/*

 * Check if the address reported by the CPU is in a format we can parse.

 * It would be possible to add code for most other cases, but all would

 * be somewhat complicated (e.g. segment offset would require an instruction

 * parser). So only support physical addresses up to page granularity for now.

 */

int mce_usable_address(struct mce *m)

bool mce_usable_address(struct mce *m)

{

	if (!(m->status & MCI_STATUS_ADDRV))

		return 0;

		return false;



	if (m->cpuvendor == X86_VENDOR_AMD)

	switch (m->cpuvendor) {

	case X86_VENDOR_AMD:

		return amd_mce_usable_address(m);



	/* Checks after this one are Intel/Zhaoxin-specific: */

	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&

	    boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)

		return 1;



	if (!(m->status & MCI_STATUS_MISCV))

		return 0;



	if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)

		return 0;



	if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)

		return 0;

	case X86_VENDOR_INTEL:

	case X86_VENDOR_ZHAOXIN:

		return intel_mce_usable_address(m);



	return 1;

	default:

		return true;

	}

}

EXPORT_SYMBOL_GPL(mce_usable_address);

arch/x86/kernel/cpu/mce/intel.c

+20 −0
Original line number Diff line number Diff line
@@ -536,3 +536,23 @@ bool intel_filter_mce(struct mce *m) 


	return false;

}



/*

 * Check if the address reported by the CPU is in a format we can parse.

 * It would be possible to add code for most other cases, but all would

 * be somewhat complicated (e.g. segment offset would require an instruction

 * parser). So only support physical addresses up to page granularity for now.

 */

bool intel_mce_usable_address(struct mce *m)

{

	if (!(m->status & MCI_STATUS_MISCV))

		return false;



	if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)

		return false;



	if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)

		return false;



	return true;

}

arch/x86/kernel/cpu/mce/internal.h

+2 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ void intel_init_cmci(void); 
void intel_init_lmce(void);

void intel_clear_lmce(void);

bool intel_filter_mce(struct mce *m);

bool intel_mce_usable_address(struct mce *m);

#else

# define cmci_intel_adjust_timer mce_adjust_timer_default

static inline bool mce_intel_cmci_poll(void) { return false; }
@@ -58,6 +59,7 @@ static inline void intel_init_cmci(void) { } 
static inline void intel_init_lmce(void) { }

static inline void intel_clear_lmce(void) { }

static inline bool intel_filter_mce(struct mce *m) { return false; }

static inline bool intel_mce_usable_address(struct mce *m) { return false; }

#endif



void mce_timer_kick(unsigned long interval);