Loading drivers/gpu/drm/nouveau/nouveau_bo.c +0 −1 Original line number Diff line number Diff line Loading @@ -433,7 +433,6 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, TTM_MEMTYPE_FLAG_CMA; man->available_caching = TTM_PL_MASK_CACHING; man->default_caching = TTM_PL_FLAG_CACHED; man->gpu_offset = dev_priv->gart_info.aper_base; break; default: NV_ERROR(dev, "Unknown GART type: %d\n", Loading drivers/gpu/drm/nouveau/nouveau_channel.c +1 −1 Original line number Diff line number Diff line Loading @@ -54,7 +54,7 @@ nouveau_channel_pushbuf_init(struct nouveau_channel *chan) * buffer resides, userspace can submit its own push buffers from * anywhere within the same memtype. */ chan->pushbuf_base = chan->pushbuf_bo->bo.mem.start << PAGE_SHIFT; chan->pushbuf_base = chan->pushbuf_bo->bo.offset; if (dev_priv->card_type >= NV_50) { if (dev_priv->card_type < NV_C0) { ret = nouveau_gpuobj_dma_new(chan, Loading drivers/gpu/drm/nouveau/nouveau_drv.c +1 −1 Original line number Diff line number Diff line Loading @@ -358,7 +358,7 @@ nouveau_pci_resume(struct pci_dev *pdev) list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); u32 offset = nv_crtc->cursor.nvbo->bo.mem.start << PAGE_SHIFT; u32 offset = nv_crtc->cursor.nvbo->bo.offset; nv_crtc->cursor.set_offset(nv_crtc, offset); nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x, Loading drivers/gpu/drm/nouveau/nouveau_notifier.c +1 −1 Original line number Diff line number Diff line Loading @@ -122,7 +122,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, target = NV_MEM_TARGET_VRAM; else target = NV_MEM_TARGET_GART; offset = chan->notifier_bo->bo.mem.start << PAGE_SHIFT; offset = chan->notifier_bo->bo.offset; } else { target = NV_MEM_TARGET_VM; offset = chan->notifier_bo->vma.offset; Loading drivers/gpu/drm/nouveau/nouveau_object.c +1 −1 Original line number Diff line number Diff line Loading @@ -768,7 +768,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_gpuobj *sem = NULL; struct nv50_display_crtc *dispc = &nv50_display(dev)->crtc[i]; u64 offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT; u64 offset = dispc->sem.bo->bo.offset; ret = nouveau_gpuobj_dma_new(chan, 0x3d, offset, 0xfff, NV_MEM_ACCESS_RW, Loading Loading
drivers/gpu/drm/nouveau/nouveau_bo.c +0 −1 Original line number Diff line number Diff line Loading @@ -433,7 +433,6 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, TTM_MEMTYPE_FLAG_CMA; man->available_caching = TTM_PL_MASK_CACHING; man->default_caching = TTM_PL_FLAG_CACHED; man->gpu_offset = dev_priv->gart_info.aper_base; break; default: NV_ERROR(dev, "Unknown GART type: %d\n", Loading
drivers/gpu/drm/nouveau/nouveau_channel.c +1 −1 Original line number Diff line number Diff line Loading @@ -54,7 +54,7 @@ nouveau_channel_pushbuf_init(struct nouveau_channel *chan) * buffer resides, userspace can submit its own push buffers from * anywhere within the same memtype. */ chan->pushbuf_base = chan->pushbuf_bo->bo.mem.start << PAGE_SHIFT; chan->pushbuf_base = chan->pushbuf_bo->bo.offset; if (dev_priv->card_type >= NV_50) { if (dev_priv->card_type < NV_C0) { ret = nouveau_gpuobj_dma_new(chan, Loading
drivers/gpu/drm/nouveau/nouveau_drv.c +1 −1 Original line number Diff line number Diff line Loading @@ -358,7 +358,7 @@ nouveau_pci_resume(struct pci_dev *pdev) list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); u32 offset = nv_crtc->cursor.nvbo->bo.mem.start << PAGE_SHIFT; u32 offset = nv_crtc->cursor.nvbo->bo.offset; nv_crtc->cursor.set_offset(nv_crtc, offset); nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x, Loading
drivers/gpu/drm/nouveau/nouveau_notifier.c +1 −1 Original line number Diff line number Diff line Loading @@ -122,7 +122,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, target = NV_MEM_TARGET_VRAM; else target = NV_MEM_TARGET_GART; offset = chan->notifier_bo->bo.mem.start << PAGE_SHIFT; offset = chan->notifier_bo->bo.offset; } else { target = NV_MEM_TARGET_VM; offset = chan->notifier_bo->vma.offset; Loading
drivers/gpu/drm/nouveau/nouveau_object.c +1 −1 Original line number Diff line number Diff line Loading @@ -768,7 +768,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_gpuobj *sem = NULL; struct nv50_display_crtc *dispc = &nv50_display(dev)->crtc[i]; u64 offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT; u64 offset = dispc->sem.bo->bo.offset; ret = nouveau_gpuobj_dma_new(chan, 0x3d, offset, 0xfff, NV_MEM_ACCESS_RW, Loading