Loading drivers/gpu/drm/nouveau/nouveau_bo.c +0 −2 Original line number Diff line number Diff line Loading @@ -138,8 +138,6 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, } nvbo->channel = NULL; if (nvbo->vma.node) nvbo->bo.offset = nvbo->vma.offset; *pnvbo = nvbo; return 0; } Loading drivers/gpu/drm/nouveau/nouveau_channel.c +1 −1 Original line number Diff line number Diff line Loading @@ -64,7 +64,7 @@ nouveau_channel_pushbuf_init(struct nouveau_channel *chan) NV_MEM_TARGET_VM, &chan->pushbuf); } chan->pushbuf_base = chan->pushbuf_bo->bo.offset; chan->pushbuf_base = chan->pushbuf_bo->vma.offset; } else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) { ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0, Loading drivers/gpu/drm/nouveau/nouveau_dma.c +1 −1 Original line number Diff line number Diff line Loading @@ -167,7 +167,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, int delta, int length) { struct nouveau_bo *pb = chan->pushbuf_bo; uint64_t offset = bo->bo.offset + delta; uint64_t offset = bo->vma.offset + delta; int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; BUG_ON(chan->dma.ib_free < 1); Loading drivers/gpu/drm/nouveau/nouveau_gem.c +5 −1 Original line number Diff line number Diff line Loading @@ -125,6 +125,7 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, static int nouveau_gem_info(struct drm_gem_object *gem, struct drm_nouveau_gem_info *rep) { struct drm_nouveau_private *dev_priv = gem->dev->dev_private; struct nouveau_bo *nvbo = nouveau_gem_object(gem); if (nvbo->bo.mem.mem_type == TTM_PL_TT) Loading @@ -133,7 +134,10 @@ nouveau_gem_info(struct drm_gem_object *gem, struct drm_nouveau_gem_info *rep) rep->domain = NOUVEAU_GEM_DOMAIN_VRAM; rep->size = nvbo->bo.mem.num_pages << PAGE_SHIFT; if (dev_priv->card_type < NV_50) rep->offset = nvbo->bo.offset; else rep->offset = nvbo->vma.offset; rep->map_handle = nvbo->bo.addr_space_offset; rep->tile_mode = nvbo->tile_mode; rep->tile_flags = nvbo->tile_flags; Loading drivers/gpu/drm/nouveau/nvc0_fbcon.c +2 −2 Original line number Diff line number Diff line Loading @@ -203,8 +203,8 @@ nvc0_fbcon_accel_init(struct fb_info *info) BEGIN_NVC0(chan, 2, NvSub2D, 0x0000, 1); OUT_RING (chan, 0x0000902d); BEGIN_NVC0(chan, 2, NvSub2D, 0x0104, 2); OUT_RING (chan, upper_32_bits(chan->notifier_bo->bo.offset)); OUT_RING (chan, lower_32_bits(chan->notifier_bo->bo.offset)); OUT_RING (chan, upper_32_bits(chan->notifier_bo->vma.offset)); OUT_RING (chan, lower_32_bits(chan->notifier_bo->vma.offset)); BEGIN_NVC0(chan, 2, NvSub2D, 0x0290, 1); OUT_RING (chan, 0); BEGIN_NVC0(chan, 2, NvSub2D, 0x0888, 1); Loading Loading
drivers/gpu/drm/nouveau/nouveau_bo.c +0 −2 Original line number Diff line number Diff line Loading @@ -138,8 +138,6 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, } nvbo->channel = NULL; if (nvbo->vma.node) nvbo->bo.offset = nvbo->vma.offset; *pnvbo = nvbo; return 0; } Loading
drivers/gpu/drm/nouveau/nouveau_channel.c +1 −1 Original line number Diff line number Diff line Loading @@ -64,7 +64,7 @@ nouveau_channel_pushbuf_init(struct nouveau_channel *chan) NV_MEM_TARGET_VM, &chan->pushbuf); } chan->pushbuf_base = chan->pushbuf_bo->bo.offset; chan->pushbuf_base = chan->pushbuf_bo->vma.offset; } else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) { ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0, Loading
drivers/gpu/drm/nouveau/nouveau_dma.c +1 −1 Original line number Diff line number Diff line Loading @@ -167,7 +167,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, int delta, int length) { struct nouveau_bo *pb = chan->pushbuf_bo; uint64_t offset = bo->bo.offset + delta; uint64_t offset = bo->vma.offset + delta; int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; BUG_ON(chan->dma.ib_free < 1); Loading
drivers/gpu/drm/nouveau/nouveau_gem.c +5 −1 Original line number Diff line number Diff line Loading @@ -125,6 +125,7 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, static int nouveau_gem_info(struct drm_gem_object *gem, struct drm_nouveau_gem_info *rep) { struct drm_nouveau_private *dev_priv = gem->dev->dev_private; struct nouveau_bo *nvbo = nouveau_gem_object(gem); if (nvbo->bo.mem.mem_type == TTM_PL_TT) Loading @@ -133,7 +134,10 @@ nouveau_gem_info(struct drm_gem_object *gem, struct drm_nouveau_gem_info *rep) rep->domain = NOUVEAU_GEM_DOMAIN_VRAM; rep->size = nvbo->bo.mem.num_pages << PAGE_SHIFT; if (dev_priv->card_type < NV_50) rep->offset = nvbo->bo.offset; else rep->offset = nvbo->vma.offset; rep->map_handle = nvbo->bo.addr_space_offset; rep->tile_mode = nvbo->tile_mode; rep->tile_flags = nvbo->tile_flags; Loading
drivers/gpu/drm/nouveau/nvc0_fbcon.c +2 −2 Original line number Diff line number Diff line Loading @@ -203,8 +203,8 @@ nvc0_fbcon_accel_init(struct fb_info *info) BEGIN_NVC0(chan, 2, NvSub2D, 0x0000, 1); OUT_RING (chan, 0x0000902d); BEGIN_NVC0(chan, 2, NvSub2D, 0x0104, 2); OUT_RING (chan, upper_32_bits(chan->notifier_bo->bo.offset)); OUT_RING (chan, lower_32_bits(chan->notifier_bo->bo.offset)); OUT_RING (chan, upper_32_bits(chan->notifier_bo->vma.offset)); OUT_RING (chan, lower_32_bits(chan->notifier_bo->vma.offset)); BEGIN_NVC0(chan, 2, NvSub2D, 0x0290, 1); OUT_RING (chan, 0); BEGIN_NVC0(chan, 2, NvSub2D, 0x0888, 1); Loading