Commit 15e8b368 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Use set_vtotal_min_max to configure OTG VTOTAL 



In multiple parts of the DCN code, we write directly to the
OTG_V_TOTAL_* registers in some OPTC functions. Let's avoid it by using
the set_vtotal_min_max.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1298d9ab

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+4 −14
Original line number Diff line number Diff line
@@ -207,10 +207,7 @@ void optc1_program_timing( 
	/* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and

	 * OTG_V_TOTAL_MIN are equal to V_TOTAL.

	 */

	REG_SET(OTG_V_TOTAL_MAX, 0,

		OTG_V_TOTAL_MAX, v_total);

	REG_SET(OTG_V_TOTAL_MIN, 0,

		OTG_V_TOTAL_MIN, v_total);

	optc->funcs->set_vtotal_min_max(optc, v_total, v_total);



	/* v_sync_start = 0, v_sync_end = v_sync_width */

	v_sync_end = patched_crtc_timing.v_sync_width;
@@ -931,11 +928,7 @@ void optc1_set_drr( 


		}



		REG_SET(OTG_V_TOTAL_MAX, 0,

			OTG_V_TOTAL_MAX, params->vertical_total_max - 1);



		REG_SET(OTG_V_TOTAL_MIN, 0,

			OTG_V_TOTAL_MIN, params->vertical_total_min - 1);

		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);



		REG_UPDATE_5(OTG_V_TOTAL_CONTROL,

				OTG_V_TOTAL_MIN_SEL, 1,
@@ -954,11 +947,7 @@ void optc1_set_drr( 
				OTG_V_TOTAL_MAX_SEL, 0,

				OTG_FORCE_LOCK_ON_EVENT, 0);



		REG_SET(OTG_V_TOTAL_MIN, 0,

			OTG_V_TOTAL_MIN, 0);



		REG_SET(OTG_V_TOTAL_MAX, 0,

			OTG_V_TOTAL_MAX, 0);

		optc->funcs->set_vtotal_min_max(optc, 0, 0);

	}

}
@@ -1577,6 +1566,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { 
		.enable_optc_clock = optc1_enable_optc_clock,

		.set_drr = optc1_set_drr,

		.get_last_used_drr_vtotal = NULL,

		.set_vtotal_min_max = optc1_set_vtotal_min_max,

		.set_static_screen_control = optc1_set_static_screen_control,

		.set_test_pattern = optc1_set_test_pattern,

		.program_stereo = optc1_program_stereo,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c

+1 −1
Original line number Diff line number Diff line
@@ -325,6 +325,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = { 
		.enable_optc_clock = optc1_enable_optc_clock,

		.set_drr = optc1_set_drr,

		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,

		.set_vtotal_min_max = optc3_set_vtotal_min_max,

		.set_static_screen_control = optc1_set_static_screen_control,

		.program_stereo = optc1_program_stereo,

		.is_stereo_left_eye = optc1_is_stereo_left_eye,
@@ -365,4 +366,3 @@ void dcn30_timing_generator_init(struct optc *optc1) 
	optc1->min_h_sync_width = 4;

	optc1->min_v_sync_width = 1;

}

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c

+0 −1
Original line number Diff line number Diff line
@@ -201,7 +201,6 @@ void optc31_set_drr( 


		// Setup manual flow control for EOF via TRIG_A

		optc->funcs->setup_manual_trigger(optc);



	} else {

		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

				OTG_SET_V_TOTAL_MIN_MASK, 0,

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

+0 −4
Original line number Diff line number Diff line
@@ -2941,11 +2941,7 @@ struct dmub_rb_cmd_get_visual_confirm_color { 
struct dmub_optc_state {

	uint32_t v_total_max;

	uint32_t v_total_min;

	uint32_t v_total_mid;

	uint32_t v_total_mid_frame_num;

	uint32_t tg_inst;

	uint32_t enable_manual_trigger;

	uint32_t clear_force_vsync;

};



struct dmub_rb_cmd_drr_update {