Commit 151bd6c5 authored by Markus Schneider-Pargmann's avatar Markus Schneider-Pargmann Committed by Ulf Hansson
Browse files

pmdomain: mediatek: Unify configuration for infracfg and smi 



Use flags to distinguish between infracfg and smi subsystem for a bus
protection configuration. It simplifies enabling/disabling and prepares
the driver for the use of another regmap for mt8365.

Signed-off-by: default avatarMarkus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Tested-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 2ec81379

drivers/pmdomain/mediatek/mt6795-pm-domains.h

+8 −8
Original line number Diff line number Diff line
@@ -46,8 +46,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = { 
		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_infracfg = {

			BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |

		.bp_cfg = {

			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |

						     MT8173_TOP_AXI_PROT_EN_MM_M1),

		},

	},
@@ -95,8 +95,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = { 
		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(13, 8),

		.sram_pdn_ack_bits = GENMASK(21, 16),

		.bp_infracfg = {

			BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |

		.bp_cfg = {

			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |

						     MT8173_TOP_AXI_PROT_EN_MFG_M0 |

						     MT8173_TOP_AXI_PROT_EN_MFG_M1 |

						     MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

+10 −10
Original line number Diff line number Diff line
@@ -22,8 +22,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_infracfg = {

			BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |

		.bp_cfg = {

			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |

						     MT8167_TOP_AXI_PROT_EN_MCU_MM),

		},

		.caps = MTK_SCPD_ACTIVE_WAKEUP,
@@ -56,8 +56,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = 0,

		.sram_pdn_ack_bits = 0,

		.bp_infracfg = {

			BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |

		.bp_cfg = {

			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |

						     MT8167_TOP_AXI_PROT_EN_MFG_EMI),

		},

	},
@@ -88,8 +88,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = 0,

		.caps = MTK_SCPD_ACTIVE_WAKEUP,

		.bp_infracfg = {

			BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |

		.bp_cfg = {

			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |

						     MT8167_TOP_AXI_PROT_EN_CONN_MCU |

						     MT8167_TOP_AXI_PROT_EN_MCU_CONN),

		},

drivers/pmdomain/mediatek/mt8173-pm-domains.h

+8 −8
Original line number Diff line number Diff line
@@ -46,8 +46,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_infracfg = {

			BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |

		.bp_cfg = {

			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |

						     MT8173_TOP_AXI_PROT_EN_MM_M1),

		},

	},
@@ -106,8 +106,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(13, 8),

		.sram_pdn_ack_bits = GENMASK(21, 16),

		.bp_infracfg = {

			BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |

		.bp_cfg = {

			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |

						     MT8173_TOP_AXI_PROT_EN_MFG_M0 |

						     MT8173_TOP_AXI_PROT_EN_MFG_M1 |

						     MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

+77 −48
Original line number Diff line number Diff line
@@ -28,9 +28,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = 0,

		.sram_pdn_ack_bits = 0,

		.bp_infracfg = {

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),

		.bp_cfg = {

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_CONN,

				    MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR,

				    MT8183_TOP_AXI_PROT_EN_STA1),

		},

	},

	[MT8183_POWER_DOMAIN_MFG_ASYNC] = {
@@ -79,11 +82,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_infracfg = {

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET,

				    MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),

		.bp_cfg = {

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_1_MFG,

				    MT8183_TOP_AXI_PROT_EN_1_SET,

				    MT8183_TOP_AXI_PROT_EN_1_CLR,

				    MT8183_TOP_AXI_PROT_EN_STA1_1),

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MFG,

				    MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR,

				    MT8183_TOP_AXI_PROT_EN_STA1),

		},

	},

	[MT8183_POWER_DOMAIN_DISP] = {
@@ -94,14 +103,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_infracfg = {

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET,

				    MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),

		},

		.bp_smi = {

			BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,

		.bp_cfg = {

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_1_DISP,

				    MT8183_TOP_AXI_PROT_EN_1_SET,

				    MT8183_TOP_AXI_PROT_EN_1_CLR,

				    MT8183_TOP_AXI_PROT_EN_STA1_1),

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_DISP,

				    MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR,

				    MT8183_TOP_AXI_PROT_EN_STA1),

			BUS_PROT_WR(SMI,

				    MT8183_SMI_COMMON_SMI_CLAMP_DISP,

				    MT8183_SMI_COMMON_CLAMP_EN_SET,

				    MT8183_SMI_COMMON_CLAMP_EN_CLR,

				    MT8183_SMI_COMMON_CLAMP_EN),
@@ -115,18 +129,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(9, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

		.bp_infracfg = {

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET,

				    MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1),

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),

			BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,

		.bp_cfg = {

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MM_CAM,

				    MT8183_TOP_AXI_PROT_EN_MM_SET,

				    MT8183_TOP_AXI_PROT_EN_MM_CLR,

				    MT8183_TOP_AXI_PROT_EN_MM_STA1),

		},

		.bp_smi = {

			BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_CAM,

				    MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR,

				    MT8183_TOP_AXI_PROT_EN_STA1),

			BUS_PROT_WR_IGN(INFRA,

					MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,

					MT8183_TOP_AXI_PROT_EN_MM_SET,

					MT8183_TOP_AXI_PROT_EN_MM_CLR,

					MT8183_TOP_AXI_PROT_EN_MM_STA1),

			BUS_PROT_WR(SMI,

				    MT8183_SMI_COMMON_SMI_CLAMP_CAM,

				    MT8183_SMI_COMMON_CLAMP_EN_SET,

				    MT8183_SMI_COMMON_CLAMP_EN_CLR,

				    MT8183_SMI_COMMON_CLAMP_EN),
@@ -140,18 +160,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(9, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

		.bp_infracfg = {

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,

		.bp_cfg = {

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MM_ISP,

				    MT8183_TOP_AXI_PROT_EN_MM_SET,

				    MT8183_TOP_AXI_PROT_EN_MM_CLR,

				    MT8183_TOP_AXI_PROT_EN_MM_STA1),

			BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,

			BUS_PROT_WR_IGN(INFRA,

					MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,

					MT8183_TOP_AXI_PROT_EN_MM_SET,

					MT8183_TOP_AXI_PROT_EN_MM_CLR,

					MT8183_TOP_AXI_PROT_EN_MM_STA1),

		},

		.bp_smi = {

			BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,

			BUS_PROT_WR(SMI,

				    MT8183_SMI_COMMON_SMI_CLAMP_ISP,

				    MT8183_SMI_COMMON_CLAMP_EN_SET,

				    MT8183_SMI_COMMON_CLAMP_EN_CLR,

				    MT8183_SMI_COMMON_CLAMP_EN),
@@ -165,8 +186,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_smi = {

			BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,

		.bp_cfg = {

			BUS_PROT_WR(SMI,

				    MT8183_SMI_COMMON_SMI_CLAMP_VDEC,

				    MT8183_SMI_COMMON_CLAMP_EN_SET,

				    MT8183_SMI_COMMON_CLAMP_EN_CLR,

				    MT8183_SMI_COMMON_CLAMP_EN),
@@ -180,8 +202,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

		.bp_smi = {

			BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,

		.bp_cfg = {

			BUS_PROT_WR(SMI,

				    MT8183_SMI_COMMON_SMI_CLAMP_VENC,

				    MT8183_SMI_COMMON_CLAMP_EN_SET,

				    MT8183_SMI_COMMON_CLAMP_EN_CLR,

				    MT8183_SMI_COMMON_CLAMP_EN),
@@ -195,22 +218,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_infracfg = {

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,

		.bp_cfg = {

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,

				    MT8183_TOP_AXI_PROT_EN_MM_SET,

				    MT8183_TOP_AXI_PROT_EN_MM_CLR,

				    MT8183_TOP_AXI_PROT_EN_MM_STA1),

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_VPU_TOP,

				    MT8183_TOP_AXI_PROT_EN_SET,

				    MT8183_TOP_AXI_PROT_EN_CLR,

				    MT8183_TOP_AXI_PROT_EN_STA1),

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,

				    MT8183_TOP_AXI_PROT_EN_MM_SET,

				    MT8183_TOP_AXI_PROT_EN_MM_CLR,

				    MT8183_TOP_AXI_PROT_EN_MM_STA1),

		},

		.bp_smi = {

			BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,

			BUS_PROT_WR(SMI,

				    MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,

				    MT8183_SMI_COMMON_CLAMP_EN_SET,

				    MT8183_SMI_COMMON_CLAMP_EN_CLR,

				    MT8183_SMI_COMMON_CLAMP_EN),
@@ -224,12 +249,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

		.bp_infracfg = {

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,

		.bp_cfg = {

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,

				    MT8183_TOP_AXI_PROT_EN_MCU_SET,

				    MT8183_TOP_AXI_PROT_EN_MCU_CLR,

				    MT8183_TOP_AXI_PROT_EN_MCU_STA1),

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,

				    MT8183_TOP_AXI_PROT_EN_MCU_SET,

				    MT8183_TOP_AXI_PROT_EN_MCU_CLR,

				    MT8183_TOP_AXI_PROT_EN_MCU_STA1),
@@ -244,12 +271,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.pwr_sta2nd_offs = 0x0184,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

		.bp_infracfg = {

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,

		.bp_cfg = {

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,

				    MT8183_TOP_AXI_PROT_EN_MCU_SET,

				    MT8183_TOP_AXI_PROT_EN_MCU_CLR,

				    MT8183_TOP_AXI_PROT_EN_MCU_STA1),

			BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,

			BUS_PROT_WR(INFRA,

				    MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,

				    MT8183_TOP_AXI_PROT_EN_MCU_SET,

				    MT8183_TOP_AXI_PROT_EN_MCU_CLR,

				    MT8183_TOP_AXI_PROT_EN_MCU_STA1),

drivers/pmdomain/mediatek/mt8186-pm-domains.h

+130 −106
Original line number Diff line number Diff line
@@ -33,20 +33,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,

					MT8186_TOP_AXI_PROT_EN_SET,

					MT8186_TOP_AXI_PROT_EN_CLR,

					MT8186_TOP_AXI_PROT_EN_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,

					MT8186_TOP_AXI_PROT_EN_SET,

					MT8186_TOP_AXI_PROT_EN_CLR,

					MT8186_TOP_AXI_PROT_EN_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),
@@ -101,12 +105,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_DIS_STEP2,

					MT8186_TOP_AXI_PROT_EN_SET,

					MT8186_TOP_AXI_PROT_EN_CLR,

					MT8186_TOP_AXI_PROT_EN_STA),
@@ -120,12 +126,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),
@@ -150,12 +158,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),
@@ -170,12 +180,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),
@@ -210,12 +222,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),
@@ -230,12 +244,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),
@@ -250,12 +266,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,

					MT8186_TOP_AXI_PROT_EN_2_SET,

					MT8186_TOP_AXI_PROT_EN_2_CLR,

					MT8186_TOP_AXI_PROT_EN_2_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,

					MT8186_TOP_AXI_PROT_EN_2_SET,

					MT8186_TOP_AXI_PROT_EN_2_CLR,

					MT8186_TOP_AXI_PROT_EN_2_STA),
@@ -268,20 +286,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.ctl_offs = 0x304,

		.pwr_sta_offs = 0x16C,

		.pwr_sta2nd_offs = 0x170,

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,

					MT8186_TOP_AXI_PROT_EN_1_SET,

					MT8186_TOP_AXI_PROT_EN_1_CLR,

					MT8186_TOP_AXI_PROT_EN_1_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,

					MT8186_TOP_AXI_PROT_EN_SET,

					MT8186_TOP_AXI_PROT_EN_CLR,

					MT8186_TOP_AXI_PROT_EN_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,

					MT8186_TOP_AXI_PROT_EN_SET,

					MT8186_TOP_AXI_PROT_EN_CLR,

					MT8186_TOP_AXI_PROT_EN_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,

					MT8186_TOP_AXI_PROT_EN_SET,

					MT8186_TOP_AXI_PROT_EN_CLR,

					MT8186_TOP_AXI_PROT_EN_STA),
@@ -320,12 +342,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 
		.pwr_sta2nd_offs = 0x170,

		.sram_pdn_bits = BIT(8),

		.sram_pdn_ack_bits = BIT(12),

		.bp_infracfg = {

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,

		.bp_cfg = {

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,

					MT8186_TOP_AXI_PROT_EN_3_SET,

					MT8186_TOP_AXI_PROT_EN_3_CLR,

					MT8186_TOP_AXI_PROT_EN_3_STA),

			BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,

			BUS_PROT_WR_IGN(INFRA,

					MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,

					MT8186_TOP_AXI_PROT_EN_3_SET,

					MT8186_TOP_AXI_PROT_EN_3_CLR,

					MT8186_TOP_AXI_PROT_EN_3_STA),