Commit 12382ad0 authored by Prathamesh Shete's avatar Prathamesh Shete Committed by Thierry Reding
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dt-bindings: gpio: Remove FSI domain ports on Tegra234 



Ports S, T, U and V are in a separate controller that is part of the FSI
domain. Remove their definitions from the MAIN controller definitions to
get rid of the confusion.

This technically breaks ABI compatibility with old device trees. However
it doesn't cause issues in practice. The GPIO pins impacted by this are
used for non-critical functionality.

Fixes: a8b10f3d ("dt-bindings: gpio: Add Tegra234 support")
Signed-off-by: default avatarPrathamesh Shete <pshete@nvidia.com>
[treding@nvidia.com: rewrite commit message]
Reviewed-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 33f2d12d

include/dt-bindings/gpio/tegra234-gpio.h

+8 −12
Original line number Diff line number Diff line
@@ -33,18 +33,14 @@ 
#define TEGRA234_MAIN_GPIO_PORT_P  14

#define TEGRA234_MAIN_GPIO_PORT_Q  15

#define TEGRA234_MAIN_GPIO_PORT_R  16

#define TEGRA234_MAIN_GPIO_PORT_S  17

#define TEGRA234_MAIN_GPIO_PORT_T  18

#define TEGRA234_MAIN_GPIO_PORT_U  19

#define TEGRA234_MAIN_GPIO_PORT_V  20

#define TEGRA234_MAIN_GPIO_PORT_X  21

#define TEGRA234_MAIN_GPIO_PORT_Y  22

#define TEGRA234_MAIN_GPIO_PORT_Z  23

#define TEGRA234_MAIN_GPIO_PORT_AC 24

#define TEGRA234_MAIN_GPIO_PORT_AD 25

#define TEGRA234_MAIN_GPIO_PORT_AE 26

#define TEGRA234_MAIN_GPIO_PORT_AF 27

#define TEGRA234_MAIN_GPIO_PORT_AG 28

#define TEGRA234_MAIN_GPIO_PORT_X  17

#define TEGRA234_MAIN_GPIO_PORT_Y  18

#define TEGRA234_MAIN_GPIO_PORT_Z  19

#define TEGRA234_MAIN_GPIO_PORT_AC 20

#define TEGRA234_MAIN_GPIO_PORT_AD 21

#define TEGRA234_MAIN_GPIO_PORT_AE 22

#define TEGRA234_MAIN_GPIO_PORT_AF 23

#define TEGRA234_MAIN_GPIO_PORT_AG 24



#define TEGRA234_MAIN_GPIO(port, offset) \

	((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)