Commit 10e96d89 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range 



Use the common smu_v11_0_set_soft_freq_limited_range.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b2785e25

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

+2 −18
Original line number Diff line number Diff line
@@ -1047,22 +1047,6 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 
	return size;

}



int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,

				      enum smu_clk_type clk_type,

				      uint32_t min, uint32_t max)

{

	struct amdgpu_device *adev = smu->adev;

	int ret;



	if (clk_type == SMU_GFXCLK)

		amdgpu_gfx_off_ctrl(adev, false);

	ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);

	if (clk_type == SMU_GFXCLK)

		amdgpu_gfx_off_ctrl(adev, true);



	return ret;

}



static int sienna_cichlid_force_clk_levels(struct smu_context *smu,

				   enum smu_clk_type clk_type, uint32_t mask)

{
@@ -1098,7 +1082,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 
		if (ret)

			goto forec_level_out;



		ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);

		ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);

		if (ret)

			goto forec_level_out;

		break;
@@ -2590,7 +2574,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 
	.mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,

	.mode1_reset = smu_v11_0_mode1_reset,

	.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,

	.set_soft_freq_limited_range = sienna_cichlid_set_soft_freq_limited_range,

	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,

	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,

	.set_thermal_range = sienna_cichlid_set_thermal_range,

};

drivers/gpu/drm/amd/powerplay/smu_internal.h

+0 −1
Original line number Diff line number Diff line
@@ -93,7 +93,6 @@ 
#define smu_asic_set_performance_level(smu, level)			smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)

#define smu_dump_pptable(smu)						smu_ppt_funcs(dump_pptable, 0, smu)

#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq)		smu_ppt_funcs(get_dpm_clk_limited, -EINVAL, smu, clk_type, dpm_level, freq)

#define smu_set_soft_freq_limited_range(smu, clk_type, min, max)	smu_ppt_funcs(set_soft_freq_limited_range, -EINVAL, smu, clk_type, min, max)

#define smu_override_pcie_parameters(smu)				smu_ppt_funcs(override_pcie_parameters, 0, smu)

#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap)	smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)

#define smu_set_thermal_range(smu, range)				smu_ppt_funcs(set_thermal_range, 0, smu, range)

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

+16 −4
Original line number Diff line number Diff line
@@ -1764,9 +1764,12 @@ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c 
	return ret;

}



int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

			    uint32_t min, uint32_t max)

int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,

					  enum smu_clk_type clk_type,

					  uint32_t min,

					  uint32_t max)

{

	struct amdgpu_device *adev = smu->adev;

	int ret = 0, clk_id = 0;

	uint32_t param;
@@ -1774,12 +1777,16 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ 
	if (clk_id < 0)

		return clk_id;



	if (clk_type == SMU_GFXCLK &&

	    adev->asic_type == CHIP_SIENNA_CICHLID)

		amdgpu_gfx_off_ctrl(adev, false);



	if (max > 0) {

		param = (uint32_t)((clk_id << 16) | (max & 0xffff));

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,

						  param, NULL);

		if (ret)

			return ret;

			goto out;

	}



	if (min > 0) {
@@ -1787,9 +1794,14 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ 
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,

						  param, NULL);

		if (ret)

			return ret;

			goto out;

	}



out:

	if (clk_type == SMU_GFXCLK &&

	    adev->asic_type == CHIP_SIENNA_CICHLID)

		amdgpu_gfx_off_ctrl(adev, true);



	return ret;

}