Commit b2785e25 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs 



As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 46a301e1

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

+1 −177
Original line number Diff line number Diff line
@@ -1182,59 +1182,6 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu) 
	return ret;

}



static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)

{

	int ret = 0, i = 0;

	uint32_t min_freq, max_freq, force_freq;

	enum smu_clk_type clk_type;



	enum smu_clk_type clks[] = {

		SMU_GFXCLK,

		SMU_MCLK,

		SMU_SOCCLK,

	};



	for (i = 0; i < ARRAY_SIZE(clks); i++) {

		clk_type = clks[i];

		ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

		if (ret)

			return ret;



		force_freq = highest ? max_freq : min_freq;

		ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);

		if (ret)

			return ret;

	}



	return ret;

}



static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)

{

	int ret = 0, i = 0;

	uint32_t min_freq, max_freq;

	enum smu_clk_type clk_type;



	enum smu_clk_type clks[] = {

		SMU_GFXCLK,

		SMU_MCLK,

		SMU_SOCCLK,

	};



	for (i = 0; i < ARRAY_SIZE(clks); i++) {

		clk_type = clks[i];

		ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

		if (ret)

			return ret;



		ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);

		if (ret)

			return ret;

	}



	return ret;

}



static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)

{

	if (!value)
@@ -1487,50 +1434,6 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long * 
	return ret;

}



static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,

					 enum amd_dpm_forced_level level,

					 uint32_t *sclk_mask,

					 uint32_t *mclk_mask,

					 uint32_t *soc_mask)

{

	struct amdgpu_device *adev = smu->adev;

	int ret = 0;

	uint32_t level_count = 0;



	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {

		if (sclk_mask)

			*sclk_mask = 0;

	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {

		if (mclk_mask)

			*mclk_mask = 0;

	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {

		if(sclk_mask) {

			amdgpu_gfx_off_ctrl(adev, false);

			ret = smu_v11_0_get_dpm_level_count(smu, SMU_SCLK, &level_count);

			amdgpu_gfx_off_ctrl(adev, true);

			if (ret)

				return ret;

			*sclk_mask = level_count - 1;

		}



		if(mclk_mask) {

			ret = smu_v11_0_get_dpm_level_count(smu, SMU_MCLK, &level_count);

			if (ret)

				return ret;

			*mclk_mask = level_count - 1;

		}



		if(soc_mask) {

			ret = smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);

			if (ret)

				return ret;

			*soc_mask = level_count - 1;

		}

	}



	return ret;

}



static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)

{

	struct smu_clocks min_clocks = {0};
@@ -1762,82 +1665,6 @@ static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t 
	return 0;

}



static int sienna_cichlid_set_performance_level(struct smu_context *smu,

					enum amd_dpm_forced_level level);



static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;

	int ret = 0;

	uint32_t sclk_freq = 0, uclk_freq = 0;



	switch (adev->asic_type) {

	/* TODO: need to set specify clk value by asic type, not support yet*/

	default:

		/* by default, this is same as auto performance level */

		return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);

	}



	ret = sienna_cichlid_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);

	if (ret)

		return ret;

	ret = sienna_cichlid_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);

	if (ret)

		return ret;



	return ret;

}



static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)

{

	int ret = 0;



	/* TODO: not support yet*/

	return ret;

}



static int sienna_cichlid_set_performance_level(struct smu_context *smu,

					enum amd_dpm_forced_level level)

{

	int ret = 0;

	uint32_t sclk_mask, mclk_mask, soc_mask;



	switch (level) {

	case AMD_DPM_FORCED_LEVEL_HIGH:

		ret = smu_force_dpm_limit_value(smu, true);

		break;

	case AMD_DPM_FORCED_LEVEL_LOW:

		ret = smu_force_dpm_limit_value(smu, false);

		break;

	case AMD_DPM_FORCED_LEVEL_AUTO:

		ret = smu_unforce_dpm_levels(smu);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:

		ret = sienna_cichlid_set_standard_performance_level(smu);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:

		ret = smu_get_profiling_clk_mask(smu, level,

						 &sclk_mask,

						 &mclk_mask,

						 &soc_mask);

		if (ret)

			return ret;

		smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);

		smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);

		smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:

		ret = sienna_cichlid_set_peak_performance_level(smu);

		break;

	case AMD_DPM_FORCED_LEVEL_MANUAL:

	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:

	default:

		break;

	}

	return ret;

}



static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,

						struct smu_temperature_range *range)

{
@@ -2706,18 +2533,15 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 
	.pre_display_config_changed = sienna_cichlid_pre_display_config_changed,

	.display_config_changed = sienna_cichlid_display_config_changed,

	.notify_smc_display_config = sienna_cichlid_notify_smc_display_config,

	.force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,

	.unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,

	.is_dpm_running = sienna_cichlid_is_dpm_running,

	.get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,

	.get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,

	.get_power_profile_mode = sienna_cichlid_get_power_profile_mode,

	.set_power_profile_mode = sienna_cichlid_set_power_profile_mode,

	.get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,

	.set_watermarks_table = sienna_cichlid_set_watermarks_table,

	.read_sensor = sienna_cichlid_read_sensor,

	.get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,

	.set_performance_level = sienna_cichlid_set_performance_level,

	.set_performance_level = smu_v11_0_set_performance_level,

	.get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,

	.display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,

	.get_power_limit = sienna_cichlid_get_power_limit,