Commit 0ce013a4 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Update VRR parameters in fastset 



We should be able to change any of the VRR parameters
during fastsets as long as we toggle VRR off at the start
and then back on at the end. The transcoder will be running
in non-VRR mode during the transition.

Co-developed-by: default avatarManasi Navare <navaremanasi@chromium.org>
Signed-off-by: default avatarManasi Navare <navaremanasi@chromium.org>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230901130440.2085-11-ville.syrjala@linux.intel.com


Reviewed-by: default avatarSean Paul <seanpaul@chromium.org>
parent 8f782270

drivers/gpu/drm/i915/display/intel_display.c

+26 −8
Original line number Diff line number Diff line
@@ -913,18 +913,32 @@ static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 
	return is_disabling(active_planes, old_crtc_state, new_crtc_state);

}



static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,

			       const struct intel_crtc_state *new_crtc_state)

{

	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||

		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||

		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||

		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||

		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;

}



static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,

			 const struct intel_crtc_state *new_crtc_state)

{

	return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||

		(new_crtc_state->vrr.enable && new_crtc_state->update_m_n);

		(new_crtc_state->vrr.enable &&

		 (new_crtc_state->update_m_n ||

		  vrr_params_changed(old_crtc_state, new_crtc_state)));

}



static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,

			  const struct intel_crtc_state *new_crtc_state)

{

	return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||

		(old_crtc_state->vrr.enable && new_crtc_state->update_m_n);

		(old_crtc_state->vrr.enable &&

		 (new_crtc_state->update_m_n ||

		  vrr_params_changed(old_crtc_state, new_crtc_state)));

}



#undef is_disabling
@@ -5374,13 +5388,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
	PIPE_CONF_CHECK_I(splitter.link_count);

	PIPE_CONF_CHECK_I(splitter.pixel_overlap);



	if (!fastset)

	if (!fastset) {

		PIPE_CONF_CHECK_BOOL(vrr.enable);

		PIPE_CONF_CHECK_I(vrr.vmin);

		PIPE_CONF_CHECK_I(vrr.vmax);

		PIPE_CONF_CHECK_I(vrr.flipline);

		PIPE_CONF_CHECK_I(vrr.pipeline_full);

		PIPE_CONF_CHECK_I(vrr.guardband);

	}



#undef PIPE_CONF_CHECK_X

#undef PIPE_CONF_CHECK_I
@@ -6586,6 +6601,9 @@ static void intel_update_crtc(struct intel_atomic_state *state, 
		if (DISPLAY_VER(i915) >= 11 &&

		    intel_crtc_needs_fastset(new_crtc_state))

			icl_set_pipe_chicken(new_crtc_state);



		if (vrr_params_changed(old_crtc_state, new_crtc_state))

			intel_vrr_set_transcoder_timings(new_crtc_state);

	}



	intel_fbc_update(state, crtc);