Commit 0cd343a4 authored by Rene Sapiens's avatar Rene Sapiens Committed by Greg Kroah-Hartman
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staging: ti dspbridge: Rename words with camel case 



The intention of this patch is to rename the remaining variables with camel
case. Variables will be renamed avoiding camel case and Hungarian notation.
The words to be renamed in this patch are:
========================================
segmentId to segmnt_id
SetPageDirty to set_page_dirty
sizeInBytes to size_in_bytes
sleepCode to sleep_code
Status to status
symName to sym_name
szVar to sz_var
Trapped_Args to trapped_args
TTBPhysAddr to ttb_phys_addr
uChirps to chirps
uChnlId to ch_id
uChnlID to ch_id
uContentSize to cont_size
uDDMAChnlId to ddma_chnl_id
uEvents to events
ulAlign to align_mask
========================================

Signed-off-by: default avatarRene Sapiens <rene.sapiens@ti.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 318b5df9

drivers/staging/tidspbridge/core/chnl_sm.c

+15 −15
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ 
#define MAILBOX_IRQ INT_MAIL_MPU_IRQ



/*  ----------------------------------- Function Prototypes */

static struct lst_list *create_chirp_list(u32 uChirps);

static struct lst_list *create_chirp_list(u32 chirps);



static void free_chirp_list(struct lst_list *lst);
@@ -709,18 +709,18 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout, 
 *  ======== bridge_chnl_get_mgr_info ========

 *      Retrieve information related to the channel manager.

 */

int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 uChnlID,

int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 ch_id,

				 OUT struct chnl_mgrinfo *mgr_info)

{

	int status = 0;

	struct chnl_mgr *chnl_mgr_obj = (struct chnl_mgr *)hchnl_mgr;



	if (mgr_info != NULL) {

		if (uChnlID <= CHNL_MAXCHANNELS) {

		if (ch_id <= CHNL_MAXCHANNELS) {

			if (hchnl_mgr) {

				/* Return the requested information: */

				mgr_info->chnl_obj =

				    chnl_mgr_obj->ap_channel[uChnlID];

				    chnl_mgr_obj->ap_channel[ch_id];

				mgr_info->open_channels =

				    chnl_mgr_obj->open_channels;

				mgr_info->dw_type = chnl_mgr_obj->dw_type;
@@ -776,7 +776,7 @@ int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 timeout, 
 */

int bridge_chnl_open(OUT struct chnl_object **chnl,

			    struct chnl_mgr *hchnl_mgr, s8 chnl_mode,

			    u32 uChnlId, CONST IN struct chnl_attr *pattrs)

			    u32 ch_id, CONST IN struct chnl_attr *pattrs)

{

	int status = 0;

	struct chnl_mgr *chnl_mgr_obj = hchnl_mgr;
@@ -794,23 +794,23 @@ int bridge_chnl_open(OUT struct chnl_object **chnl, 
		if (!hchnl_mgr) {

			status = -EFAULT;

		} else {

			if (uChnlId != CHNL_PICKFREE) {

				if (uChnlId >= chnl_mgr_obj->max_channels)

			if (ch_id != CHNL_PICKFREE) {

				if (ch_id >= chnl_mgr_obj->max_channels)

					status = -ECHRNG;

				else if (chnl_mgr_obj->ap_channel[uChnlId] !=

				else if (chnl_mgr_obj->ap_channel[ch_id] !=

					 NULL)

					status = -EALREADY;

			} else {

				/* Check for free channel */

				status =

				    search_free_channel(chnl_mgr_obj, &uChnlId);

				    search_free_channel(chnl_mgr_obj, &ch_id);

			}

		}

	}

	if (DSP_FAILED(status))

		goto func_end;



	DBC_ASSERT(uChnlId < chnl_mgr_obj->max_channels);

	DBC_ASSERT(ch_id < chnl_mgr_obj->max_channels);

	/* Create channel object: */

	pchnl = kzalloc(sizeof(struct chnl_object), GFP_KERNEL);

	if (!pchnl) {
@@ -846,7 +846,7 @@ int bridge_chnl_open(OUT struct chnl_object **chnl, 
		    pchnl->free_packets_list) {

			/* Initialize CHNL object fields: */

			pchnl->chnl_mgr_obj = chnl_mgr_obj;

			pchnl->chnl_id = uChnlId;

			pchnl->chnl_id = ch_id;

			pchnl->chnl_mode = chnl_mode;

			pchnl->user_event = sync_event;

			pchnl->sync_event = sync_event;
@@ -926,13 +926,13 @@ int bridge_chnl_register_notify(struct chnl_object *chnl_obj, 
 *  Purpose:

 *      Initialize a queue of channel I/O Request/Completion packets.

 *  Parameters:

 *      uChirps:    Number of Chirps to allocate.

 *      chirps:     Number of Chirps to allocate.

 *  Returns:

 *      Pointer to queue of IRPs, or NULL.

 *  Requires:

 *  Ensures:

 */

static struct lst_list *create_chirp_list(u32 uChirps)

static struct lst_list *create_chirp_list(u32 chirps)

{

	struct lst_list *chirp_list;

	struct chnl_irp *chnl_packet_obj;
@@ -943,14 +943,14 @@ static struct lst_list *create_chirp_list(u32 uChirps) 
	if (chirp_list) {

		INIT_LIST_HEAD(&chirp_list->head);

		/* Make N chirps and place on queue. */

		for (i = 0; (i < uChirps)

		for (i = 0; (i < chirps)

		     && ((chnl_packet_obj = make_new_chirp()) != NULL); i++) {

			lst_put_tail(chirp_list,

				     (struct list_head *)chnl_packet_obj);

		}



		/* If we couldn't allocate all chirps, free those allocated: */

		if (i != uChirps) {

		if (i != chirps) {

			free_chirp_list(chirp_list);

			chirp_list = NULL;

		}

drivers/staging/tidspbridge/core/tiomap3430.c

+2 −2
Original line number Diff line number Diff line
@@ -1507,7 +1507,7 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt, 
						"0x%x\n", paddr, ul_num_bytes);

					bad_page_dump(paddr, pg);

				} else {

					SetPageDirty(pg);

					set_page_dirty(pg);

					page_cache_release(pg);

				}

				paddr += HW_PAGE_SIZE4KB;
@@ -1571,7 +1571,7 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt, 
						"0x%x\n", paddr, ul_num_bytes);

					bad_page_dump(paddr, pg);

				} else {

					SetPageDirty(pg);

					set_page_dirty(pg);

					page_cache_release(pg);

				}

			}

drivers/staging/tidspbridge/hw/hw_mmu.c

+2 −2
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr) 
	return status;

}



hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 TTBPhysAddr)

hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)

{

	hw_status status = RET_OK;

	u32 load_ttb;
@@ -268,7 +268,7 @@ hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 TTBPhysAddr) 
	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,

			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);



	load_ttb = TTBPhysAddr & ~0x7FUL;

	load_ttb = ttb_phys_addr & ~0x7FUL;

	/* write values to register */

	MMUMMU_TTB_WRITE_REGISTER32(base_address, load_ttb);

drivers/staging/tidspbridge/hw/hw_mmu.h

+1 −1
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ extern hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, 


/* Set the TT base address */

extern hw_status hw_mmu_ttb_set(const void __iomem *base_address,

				u32 TTBPhysAddr);

				u32 ttb_phys_addr);



extern hw_status hw_mmu_twl_enable(const void __iomem *base_address);

drivers/staging/tidspbridge/include/dspbridge/dbdefs.h

+2 −2
Original line number Diff line number Diff line
@@ -94,8 +94,8 @@ 
#define DSPWORDSIZE     sizeof(DSPWORD)



/* Success & Failure macros */

#define DSP_SUCCEEDED(Status)      likely((s32)(Status) >= 0)

#define DSP_FAILED(Status)         unlikely((s32)(Status) < 0)

#define DSP_SUCCEEDED(status)      likely((s32)(status) >= 0)

#define DSP_FAILED(status)         unlikely((s32)(status) < 0)



/* Power control enumerations */

#define PROC_PWRCONTROL             0x8070