Unverified Commit 0a371981 authored by Boris Brezillon's avatar Boris Brezillon Committed by Tudor Ambarus
Browse files

mtd: spi-nor: Move ISSI bits out of core.c 



Create a SPI NOR manufacturer driver for ISSI chips, and move the
ISSI definitions outside of core.c.

Signed-off-by: default avatarBoris Brezillon <bbrezillon@kernel.org>
Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
parent aa635187

drivers/mtd/spi-nor/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -8,4 +8,5 @@ spi-nor-objs += everspin.o 
spi-nor-objs			+= fujitsu.o

spi-nor-objs			+= gigadevice.o

spi-nor-objs			+= intel.o

spi-nor-objs			+= issi.o

obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o

drivers/mtd/spi-nor/core.c

+1 −65
Original line number Diff line number Diff line
@@ -2007,28 +2007,6 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 
	return 0;

}



static int

is25lp256_post_bfpt_fixups(struct spi_nor *nor,

			   const struct sfdp_parameter_header *bfpt_header,

			   const struct sfdp_bfpt *bfpt,

			   struct spi_nor_flash_parameter *params)

{

	/*

	 * IS25LP256 supports 4B opcodes, but the BFPT advertises a

	 * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.

	 * Overwrite the address width advertised by the BFPT.

	 */

	if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==

		BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)

		nor->addr_width = 4;



	return 0;

}



static struct spi_nor_fixups is25lp256_fixups = {

	.post_bfpt = is25lp256_post_bfpt_fixups,

};



static int

mx25l25635_post_bfpt_fixups(struct spi_nor *nor,

			    const struct sfdp_parameter_header *bfpt_header,
@@ -2066,35 +2044,6 @@ static struct spi_nor_fixups mx25l25635_fixups = { 
 * old entries may be missing 4K flag.

 */

static const struct flash_info spi_nor_ids[] = {

	/* ISSI */

	{ "is25cd512",  INFO(0x7f9d20, 0, 32 * 1024,   2, SECT_4K) },

	{ "is25lq040b", INFO(0x9d4013, 0, 64 * 1024,   8,

			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25lp016d", INFO(0x9d6015, 0, 64 * 1024,  32,

			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25lp080d", INFO(0x9d6014, 0, 64 * 1024,  16,

			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25lp032",  INFO(0x9d6016, 0, 64 * 1024,  64,

			SECT_4K | SPI_NOR_DUAL_READ) },

	{ "is25lp064",  INFO(0x9d6017, 0, 64 * 1024, 128,

			SECT_4K | SPI_NOR_DUAL_READ) },

	{ "is25lp128",  INFO(0x9d6018, 0, 64 * 1024, 256,

			SECT_4K | SPI_NOR_DUAL_READ) },

	{ "is25lp256",  INFO(0x9d6019, 0, 64 * 1024, 512,

			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			SPI_NOR_4B_OPCODES)

			.fixups = &is25lp256_fixups },

	{ "is25wp032",  INFO(0x9d7016, 0, 64 * 1024,  64,

			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25wp064",  INFO(0x9d7017, 0, 64 * 1024, 128,

			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25wp128",  INFO(0x9d7018, 0, 64 * 1024, 256,

			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,

			    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			    SPI_NOR_4B_OPCODES)

		       .fixups = &is25lp256_fixups },



	/* Macronix */

	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1, SECT_4K) },

	{ "mx25l2005a",  INFO(0xc22012, 0, 64 * 1024,   4, SECT_4K) },
@@ -2175,11 +2124,6 @@ static const struct flash_info spi_nor_ids[] = { 
			     SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |

			     SPI_NOR_4B_OPCODES) },



	/* PMC */

	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },

	{ "pm25lv010",   INFO(0,        0, 32 * 1024,    4, SECT_4K_PMC) },

	{ "pm25lq032",   INFO(0x7f9d46, 0, 64 * 1024,   64, SECT_4K) },



	/* Spansion/Cypress -- single (large) sector size only, at least

	 * for the chips listed here (without boot sectors).

	 */
@@ -2368,6 +2312,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = { 
	&spi_nor_fujitsu,

	&spi_nor_gigadevice,

	&spi_nor_intel,

	&spi_nor_issi,

};



static const struct flash_info *
@@ -3147,11 +3092,6 @@ static int spi_nor_setup(struct spi_nor *nor, 
	return nor->params.setup(nor, hwcaps);

}



static void issi_set_default_init(struct spi_nor *nor)

{

	nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;

}



static void macronix_set_default_init(struct spi_nor *nor)

{

	nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
@@ -3185,10 +3125,6 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor) 
{

	/* Init flash parameters based on MFR */

	switch (JEDEC_MFR(nor->info)) {

	case SNOR_MFR_ISSI:

		issi_set_default_init(nor);

		break;



	case SNOR_MFR_MACRONIX:

		macronix_set_default_init(nor);

		break;

drivers/mtd/spi-nor/core.h

+1 −0
Original line number Diff line number Diff line
@@ -174,6 +174,7 @@ extern const struct spi_nor_manufacturer spi_nor_everspin; 
extern const struct spi_nor_manufacturer spi_nor_fujitsu;

extern const struct spi_nor_manufacturer spi_nor_gigadevice;

extern const struct spi_nor_manufacturer spi_nor_intel;

extern const struct spi_nor_manufacturer spi_nor_issi;



int spi_nor_write_enable(struct spi_nor *nor);

int spi_nor_write_disable(struct spi_nor *nor);

drivers/mtd/spi-nor/issi.c

0 → 100644
+83 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2005, Intec Automation Inc.

 * Copyright (C) 2014, Freescale Semiconductor, Inc.

 */



#include <linux/mtd/spi-nor.h>



#include "core.h"



static int

is25lp256_post_bfpt_fixups(struct spi_nor *nor,

			   const struct sfdp_parameter_header *bfpt_header,

			   const struct sfdp_bfpt *bfpt,

			   struct spi_nor_flash_parameter *params)

{

	/*

	 * IS25LP256 supports 4B opcodes, but the BFPT advertises a

	 * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.

	 * Overwrite the address width advertised by the BFPT.

	 */

	if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==

		BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)

		nor->addr_width = 4;



	return 0;

}



static struct spi_nor_fixups is25lp256_fixups = {

	.post_bfpt = is25lp256_post_bfpt_fixups,

};



static const struct flash_info issi_parts[] = {

	/* ISSI */

	{ "is25cd512",  INFO(0x7f9d20, 0, 32 * 1024,   2, SECT_4K) },

	{ "is25lq040b", INFO(0x9d4013, 0, 64 * 1024,   8,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25lp016d", INFO(0x9d6015, 0, 64 * 1024,  32,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25lp080d", INFO(0x9d6014, 0, 64 * 1024,  16,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25lp032",  INFO(0x9d6016, 0, 64 * 1024,  64,

			     SECT_4K | SPI_NOR_DUAL_READ) },

	{ "is25lp064",  INFO(0x9d6017, 0, 64 * 1024, 128,

			     SECT_4K | SPI_NOR_DUAL_READ) },

	{ "is25lp128",  INFO(0x9d6018, 0, 64 * 1024, 256,

			     SECT_4K | SPI_NOR_DUAL_READ) },

	{ "is25lp256",  INFO(0x9d6019, 0, 64 * 1024, 512,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			     SPI_NOR_4B_OPCODES)

		.fixups = &is25lp256_fixups },

	{ "is25wp032",  INFO(0x9d7016, 0, 64 * 1024,  64,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25wp064",  INFO(0x9d7017, 0, 64 * 1024, 128,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25wp128",  INFO(0x9d7018, 0, 64 * 1024, 256,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,

			    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			    SPI_NOR_4B_OPCODES)

		.fixups = &is25lp256_fixups },



	/* PMC */

	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },

	{ "pm25lv010",   INFO(0,        0, 32 * 1024,    4, SECT_4K_PMC) },

	{ "pm25lq032",   INFO(0x7f9d46, 0, 64 * 1024,   64, SECT_4K) },

};



static void issi_default_init(struct spi_nor *nor)

{

	nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;

}



static const struct spi_nor_fixups issi_fixups = {

	.default_init = issi_default_init,

};



const struct spi_nor_manufacturer spi_nor_issi = {

	.name = "issi",

	.parts = issi_parts,

	.nparts = ARRAY_SIZE(issi_parts),

	.fixups = &issi_fixups,

};